inclusion because
pmp_is_in_range(env, i, addr + size) returns 0 whereas
pmp_is_in_range(env, i, addr) returns 1.
Signed-off-by: Dayeol Lee
Reviewed-by: Alistair Francis
Reviewed-by: Michael Clark
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 2 +-
1 file
/palmer-dabbelt/qemu.git tags/riscv-for-master-4.1-sf1
for you to fetch changes up to c08a8317e31033ec76b8460a0b75cbcdaeeef481:
hw/riscv: Load OpenSBI as the default firmware (2019-06-27 02:47:06 -0700)
RISC-V Patches for the 4.1
From: Nathaniel Graff
Writes to the SiFive PRCI registers are preserved while leaving the
ready bits set for the HFX/HFR oscillators and the lock bit set for the
PLL.
Signed-off-by: Nathaniel Graff
Reviewed-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c
On Wed, 26 Jun 2019 01:30:35 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/26/19 10:25 AM, Palmer Dabbelt wrote:
You misunderstand. The code is exactly correct as-is. The alignment check
happens implicitly as a part of the softmmu tlb resolution.
Sorry, I thought you said it wasn't
On Tue, 25 Jun 2019 23:54:06 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Tue, Jun 25, 2019 at 5:57 PM Palmer Dabbelt wrote:
On Mon, 24 Jun 2019 16:03:20 PDT (-0700), finte...@gmail.com wrote:
> Apparently my previous message didn't make it out onto the list (sorry
> abo
On Wed, 26 Jun 2019 00:48:51 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/26/19 8:07 AM, Palmer Dabbelt wrote:
On Tue, 25 Jun 2019 08:36:28 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/24/19 8:08 PM, Joel Sing wrote:
Regarding the alignment for reservations
On Tue, 25 Jun 2019 23:58:34 PDT (-0700), bmeng...@gmail.com wrote:
On Wed, Jun 26, 2019 at 4:23 AM Jonathan Behrens wrote:
I just did some testing on a HiFive Unleashed board and can confirm what
you are saying. The low 5 bits of both mcounteren and scounteren are
writable (if you try to
On Tue, 25 Jun 2019 18:47:33 PDT (-0700), bmeng...@gmail.com wrote:
Hi,
On Fri, Jun 7, 2019 at 2:46 AM Alistair Francis wrote:
On Thu, Jun 6, 2019 at 5:55 AM Bin Meng wrote:
>
> On Thu, May 30, 2019 at 11:36 AM Bin Meng wrote:
> >
> > Hi Alistair,
> >
> > On Thu, May 30, 2019 at 11:14 AM
On Tue, 25 Jun 2019 18:47:15 PDT (-0700), bmeng...@gmail.com wrote:
Hi,
On Sat, May 18, 2019 at 5:34 AM Alistair Francis
wrote:
On Fri, 2019-05-17 at 08:51 -0700, Bin Meng wrote:
> At present the cpu, plic and ethclk nodes' phandles are hard-coded
> to 1/2/3 in DT. If we configure more than
On Fri, 17 May 2019 14:35:56 PDT (-0700), Alistair Francis wrote:
On Fri, 2019-05-17 at 08:51 -0700, Bin Meng wrote:
At present the PLIC is instantiated to support only one hart, while
the machine allows at most 4 harts to be created. When more than 1
hart is configured, PLIC needs to
and everything
will work. They can also override the firmware with their own using
the -bios option. Using "-bios none" will result in no firmware being
loaded (as it is today).
@Palmer Dabbelt can this go in your 4.1 PR? It has been reviewed and tested.
I don't see any reason why not. It's top
On Tue, 25 Jun 2019 08:20:55 PDT (-0700), alistai...@gmail.com wrote:
On Tue, Jun 25, 2019 at 3:09 AM Palmer Dabbelt wrote:
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR
On Tue, 25 Jun 2019 08:39:21 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/24/19 8:08 PM, Joel Sing wrote:
From 8ef31a2ce8ef1cbeee92995a0b2994f480e9bb6d Mon Sep 17 00:00:00 2001
From: Joel Sing
Date: Tue, 25 Jun 2019 02:44:24 +1000
Subject: [PATCH] Clear load reservations on qemu riscv
On Tue, 25 Jun 2019 08:36:28 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/24/19 8:08 PM, Joel Sing wrote:
Regarding the alignment for reservations, the
specification does require this, although I do not recall seeing any enforcement
of this by qemu itself.
Ah, I see it now.
On Mon, 24 Jun 2019 16:41:44 PDT (-0700), Atish Patra wrote:
Currently, there is no cpu topology defined in RISC-V.
Define a device tree node that clearly describes the
entire topology. This saves the trouble of scanning individual
cache to figure out the topology.
Here is the linux kernel
/cpu.c| 1 +
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c | 16
target/riscv/pmp.c| 2 +-
5 files changed, 54 insertions(+), 18 deletions(-)
Reviewed-by: Palmer Dabbelt
1 and 4 were already in, so I'm leaving them towards the front of the queue
The various CSR instructions have been split out of the base ISA as part
of the ratification process. This patch adds a Zicsr argument, which
disables all the CSR instructions.
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target/riscv/csr.c | 5 +
3
fence.i has been split out of the base ISA as part of the ratification
process. This patch adds a Zifencei argument, which disables the
fence.i instruction.
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 1 +
target/riscv/cpu.h | 1 +
target
On Mon, 24 Jun 2019 16:16:30 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Jun 24, 2019 at 2:31 AM Palmer Dabbelt wrote:
On Mon, 17 Jun 2019 18:31:25 PDT (-0700), Alistair Francis wrote:
> For completeness let's add Zifencei and Zicsr as command line options,
> even though they
unters.
On Fri, Jun 14, 2019 at 7:52 AM Palmer Dabbelt wrote:
On Tue, 28 May 2019 11:30:20 PDT (-0700), jonat...@fintelia.io wrote:
> Currently mcounteren.TM acts as though it is hardwired to zero, even
though QEMU allows it to be set. This change resolves the issue by allowing
reads to the time
| 19 ++---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c| 13 +++-
.../riscv/insn_trans/trans_privileged.inc.c | 2 +-
6 files changed, 71 insertions(+), 44 deletions(-)
Aside from the comments on 3 and 9
Reviewed-by: Palme
I'm missing something, I think these two
should do it:
From 6d645eb1e8ba4d16431af40bf04e5c165475bf5a Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt
Date: Mon, 24 Jun 2019 01:59:05 -0700
Subject: [PATCH 1/2] RISC-V: Add support for the Zifencei extension
fence.i has been split out of the base
U never tick (legal according to the spec).
Signed-off-by: Alistair Francis
[Palmer: Fix counter access semantics, change commit message to indicate
the behavior is fully emulated.]
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
diff --git a/target/riscv/cpu_bits.h b/targe
On Mon, Jun 17, 2019 at 4:53 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/16/19 12:19 PM, Joel Sing wrote:
> > +/*
> > + * Clear the load reservation, since an SC must fail if there is
> > + * an SC to any address, in between an LR and SC pair.
> > + */
> > +
On Fri, 21 Jun 2019 17:23:44 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Jun 20, 2019 at 7:49 PM Palmer Dabbelt wrote:
On Wed, 19 Jun 2019 07:19:38 PDT (-0700), alistai...@gmail.com wrote:
> On Wed, Jun 19, 2019 at 3:58 AM Palmer Dabbelt wrote:
>>
>> On Mon, 17 Jun 20
On Thu, 20 Jun 2019 22:40:24 PDT (-0700), bmeng...@gmail.com wrote:
Hi Palmer,
On Fri, Jun 21, 2019 at 10:53 AM Palmer Dabbelt wrote:
On Wed, 19 Jun 2019 06:42:21 PDT (-0700), bmeng...@gmail.com wrote:
> Hi Alistair,
>
> On Tue, Jun 18, 2019 at 1:15 AM Alistair Francis wrote:
>
On Wed, 19 Jun 2019 06:42:21 PDT (-0700), bmeng...@gmail.com wrote:
Hi Alistair,
On Tue, Jun 18, 2019 at 1:15 AM Alistair Francis wrote:
On Fri, Jun 14, 2019 at 8:30 AM Bin Meng wrote:
>
> This adds a reset opcode for sifive_test device to trigger a system
> reset for testing purpose.
>
>
On Wed, 19 Jun 2019 07:19:38 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Jun 19, 2019 at 3:58 AM Palmer Dabbelt wrote:
On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
> Based-on:
>
> Now that the RISC-V spec has started to be ratified let's update o
On Mon, 17 Jun 2019 18:31:00 PDT (-0700), Alistair Francis wrote:
Based-on:
Now that the RISC-V spec has started to be ratified let's update our
QEMU implementation. There are a few things going on here:
- Add priv version 1.11.0 to QEMU
- This is the ratified version of the Privledge
On Mon, 17 Jun 2019 15:38:45 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/14/19 10:11 AM, Alex Bennée wrote:
+++ b/target/riscv/translate.c
@@ -793,7 +793,7 @@ static void riscv_tr_translate_insn(DisasContextBase
*dcbase, CPUState *cpu)
DisasContext *ctx = container_of(dcbase,
On Fri, 14 Jun 2019 05:25:50 PDT (-0700), phi...@redhat.com wrote:
On 6/14/19 2:08 PM, Palmer Dabbelt wrote:
Coverity pointed out a memory leak in riscv_sifive_e_soc_realize(),
where a pair of recently added MemoryRegion instances would not be freed
if there were errors elsewhere
in SiFiveESoCState, so instead we just include them within
the struct.
Thanks to Peter for pointing out the bug and suggesting the fix!
Fixes: 30efbf330a45 ("SiFive RISC-V GPIO Device")
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_e.c | 12 +---
include/hw/riscv/sifiv
On Thu, 30 May 2019 03:57:12 PDT (-0700), Peter Maydell wrote:
On Sun, 26 May 2019 at 02:10, Palmer Dabbelt wrote:
From: Fabien Chouteau
QEMU model of the GPIO device on the SiFive E300 series SOCs.
The pins are not used by a board definition yet, however this
implementation can already
On Tue, 28 May 2019 11:30:20 PDT (-0700), jonat...@fintelia.io wrote:
Currently mcounteren.TM acts as though it is hardwired to zero, even though
QEMU allows it to be set. This change resolves the issue by allowing reads to
the time and timeh control registers when running in a privileged mode
On Fri, 17 May 2019 15:10:56 PDT (-0700), Alistair Francis wrote:
This should be the last series bringing the patches from the RISC-V fork
into mainline QEMU.
Dayeol Lee (1):
target/riscv: Fix PMP range boundary address bug
Michael Clark (3):
disas/riscv: Disassemble reserved compressed
+env->badaddr = addr;
+riscv_raise_exception(>env, cs->exception_index, GETPC());
+}
+
void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int mmu_idx,
uintptr_t retaddr)
Reviewed-by: Palmer Dabbelt
On Fri, 17 May 2019 15:11:04 PDT (-0700), Alistair Francis wrote:
From: Michael Clark
The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.
Author: Wladimir J. van der Laan
I'm not sure what this tag is supposed to mean. If this is the
On Fri, 17 May 2019 15:11:01 PDT (-0700), Alistair Francis wrote:
From: Michael Clark
Due to the design of the disassembler, the immediate is not
known during decoding of the opcode; so to handle compressed
encodings with reserved immediate values (non-zero), we need
to add an additional check
On Thu, 06 Jun 2019 19:50:57 PDT (-0700), richard.hender...@linaro.org wrote:
Also, unless I'm misunderstanding something our implementation of LR/SC is
pretty broken. We're just using a CAS to check if the value changed, which
suffers from the ABA problem that LR/SC is there to fix in the
On Thu, 06 Jun 2019 16:22:47 PDT (-0700), alistai...@gmail.com wrote:
Hello,
As a test of the waters, how would the QEMU community feel about
including the RISC-V OpenSBI project as a ROM submodule?
The idea would be to have OpenSBI (similar to ATF for ARM and a BIOS
for x86) included by
On Wed, 05 Jun 2019 13:59:53 PDT (-0700), ma...@decred.org wrote:
Joel is on vacation so here it is again.
Begin forwarded message:
From: Alistair Francis
Subject: Re: [j...@sing.id.au: atomic failures on qemu-system-riscv64]
Date: June 5, 2019 at 7:19:53 PM GMT+1
To: "j...@sing.id.au" ,
From: Nathaniel Graff
Writes to the SiFive PRCI registers are preserved while leaving the
ready bits set for the HFX/HFR oscillators and the lock bit set for the
PLL.
Signed-off-by: Nathaniel Graff
Reviewed-by: Michael Clark
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_prci.c
target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -229,6 +229,17 @@ typedef struct RISCVCPU {
/* Configuration Settings */
struct {
+bool ext_i;
+bool ext_e;
+bool ext_g;
+bool ext_m;
+bool ext_a;
+bool ext_f;
+bool ext_d;
+bool ext_c;
+bool ext_s;
+bool ext_u;
+
char *priv_spec;
char *user_spec;
bool mmu;
Reviewed-by: Palmer Dabbelt
On Tue, 30 Apr 2019 10:36:01 PDT (-0700), finte...@gmail.com wrote:
Currently mcounteren.TM acts as though it is hardwired to zero, even though
QEMU allows it to be set. This change resolves the issue by allowing reads
to the time and timeh control registers when running in a privileged mode
Chouteau
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
Makefile.objs | 1 +
hw/riscv/Makefile.objs | 1 +
hw/riscv/sifive_e.c| 28 ++-
hw/riscv/sifive_gpio.c | 388 +
hw/riscv/trace-events
From: Jonathan Behrens
The 'sfence.vma' instruction is privileged, and should only ever be allowed
when executing in supervisor mode or higher.
Signed-off-by: Jonathan Behrens
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv
From: Richard Henderson
The generated functions are only used within translate.c
and do not need to be global, or declared.
Signed-off-by: Richard Henderson
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 8
target/riscv/translate.c | 3
stepping handling in places where it was previously ignored such as jalr
and system branch instructions (ecall, mret, sret, etc.).
Signed-off-by: Fabien Chouteau
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
.../riscv/insn_trans
From: Richard Henderson
Special handling for IMM==0 is the only difference between
RVC shifti and RVI shifti. This can be handled with !function.
Signed-off-by: Richard Henderson
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode | 12
From: Richard Henderson
The tcg_gen_fooi_tl functions have some immediate constant
folding built in, which match up with some of the riscv asm
builtin macros, like mv and not.
Signed-off-by: Richard Henderson
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv
From: Alistair Francis
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
linux-user/riscv/target_elf.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/linux-user/riscv/target_elf.h b/linux-user/riscv/target_elf.h
index a6716a6aac23..9dd65652ee45 100644
--- a/linux-user
From: Richard Henderson
These extra spaces make the "-d op" dump look weird.
Signed-off-by: Richard Henderson
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/ta
From: Alistair Francis
These can now be specified via the command line so we no longer need
these.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
qemu-deprecated.texi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/qemu
From: Richard Henderson
This eliminates all functions in insn_trans/trans_rvc.inc.c,
so the entire file can be removed.
Signed-off-by: Richard Henderson
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/Makefile.objs | 9 +-
target/riscv/insn16-32
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 49 ++
target/riscv/cpu.h | 8
2 files changed, 57 insertions(+)
diff --git a/target/riscv/cpu.c b
From: Jonathan Behrens
Signed-off-by: Jonathan Behrens
Reviewed-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index fc4c6b306e13..352646303420 100644
From: Alistair Francis
The requirement of holding the iothread_mutex is burdersome when
swapping the background and foreground registers in the Hypervisor
extension. To avoid the requrirement let's set the interrupt
asynchronously.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Igor Mammedov
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 352646303420..84d94d0c42d8 100644
--- a/hw/riscv
The following changes since commit a7b21f6762a2d6ec08106d8a7ccb11829914523f:
Merge remote-tracking branch
'remotes/vivier2/tags/linux-user-for-4.1-pull-request' into staging (2019-05-24
12:47:49 +0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 945aa8dbb851
From: Alistair Francis
No functional change, just making the code easier to read.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv
Dabbelt
Signed-off-by: Palmer Dabbelt
---
include/hw/riscv/virt.h | 4 ++--
qemu-deprecated.texi| 9 +
target/riscv/cpu.c | 14 ++
target/riscv/cpu.h | 2 ++
4 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/include/hw/riscv/virt.h b/include/hw
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 10 +++---
target/riscv/translate.c | 18 ++
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/target/riscv
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviwed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 52c21699774f
From: Alistair Francis
Signed-off-by: Alistair Francis
Revieweb-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f9d8d150e012
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 7180fccf54f9..945aa8dbb851
From: Richard Henderson
This eliminates about half of the complicated decode
bits within insn_trans/trans_rvc.inc.c.
Signed-off-by: Richard Henderson
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16.decode | 29 +---
target/riscv
From: Alistair Francis
Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target
From: Alistair Francis
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu_bits.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index a179137bc1f2..dc9d53d4becf
-by: Igor Mammedov
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/spike.c | 106 ++-
qemu-deprecated.texi | 6 +++
2 files changed, 111 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index
s both of those requirements.
Signed-off-by: Jonathan Behrens
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e6d68a99560d..0f51c7eae241 100644
---
From: Richard Henderson
C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved
operands that were not diagnosed.
Signed-off-by: Richard Henderson
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn16-64.decode | 10 --
target/riscv/insn16.decode
From: Jonathan Behrens
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
Signed-off-by: Jonathan Behrens
Reviewed-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
pc_perm {
abi_int __key; /* Key. */
--
2.17.2
Reviewed-by: Palmer Dabbelt
I'm assuming this is going in through someone else's tree, so I'm not going to
pick it up into mine.
On Wed, 08 May 2019 10:38:35 PDT (-0700), jonat...@fintelia.io wrote:
There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857
Signed-off-by: Jonathan Behrens
---
target/riscv/csr.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
, ret_value, new_value,
+ write_mask & env->mideleg & sip_writable_mask);
+*ret_value &= env->mideleg;
+return ret;
}
/* Supervisor Protection and Translation */
Reviewed-by: Palmer Dabbelt
Thanks!
On Mon, 06 May 2019 08:52:43 PDT (-0700), finte...@gmail.com wrote:
According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
register are read-only." Further, if an interrupt is not delegated to mode
x,
then "the corresponding bits in xip [...] should appear to be hardwired to
On Thu, 25 Apr 2019 10:32:43 PDT (-0700), richard.hender...@linaro.org wrote:
On 4/25/19 10:26 AM, Richard Henderson wrote:
{
+ illegal 011 0 - 0 01 # c.addi16sp, RES nzimm=0
addi011 . 00010 . 01 @c_addi16sp
lui 011 . . . 01
On Thu, 25 Apr 2019 10:26:35 PDT (-0700), richard.hender...@linaro.org wrote:
---
target/riscv/translate.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d1f599a92d..009c146e8f 100644
---
On Thu, 25 Apr 2019 09:50:41 PDT (-0700), richard.hender...@linaro.org wrote:
On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
# *** RV64C Standard Extension (Quadrant 2) ***
-c_slli 000 . . . 10 @c_shift2
+slli 000 . . . 10 @c_shift2
This is another one
On Thu, 25 Apr 2019 09:23:56 PDT (-0700), richard.hender...@linaro.org wrote:
On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
Thanks! I'm happy taking this as it stands, since all those decode issues I
pointed out aren't regressions in this patch set. Let me know if you want to
fix those or if you
On Fri, 19 Apr 2019 16:05:35 PDT (-0700), alistai...@gmail.com wrote:
On Mon, Apr 15, 2019 at 5:46 PM Jonathan Behrens wrote:
For any chip that has a CLINT, we want the frequency of the time register and
the frequency of the CLINT to match. That frequency, SIFIVE_CLINT_TIMEBASE_FREQ
On Wed, 10 Apr 2019 09:29:11 PDT (-0700), finte...@gmail.com wrote:
Unless I'm missing something, the virt board doesn't support HTIF and
should not be including this header.
Jonathan
Signed-off-by: Jonathan Behrens
---
hw/riscv/virt.c | 1 -
1 file changed, 1 deletion(-)
diff --git
On Sun, 31 Mar 2019 20:11:47 PDT (-0700), richard.hender...@linaro.org wrote:
There's new support in decodetree for pattern groups.
I believe that patch 5, or something close to it, was
posted as an RFC as part of the original pattern group
patch set, but this cleans that up further.
r~
l(DisasContext *ctx, arg_i *a,
+ void (*func)(TCGv, TCGv, TCGv))
{
TCGv source1, source2;
source1 = tcg_temp_new();
Reviewed-by: Palmer Dabbelt
100 1 . . 10 @cr
+}
fsd 101 .. . 10 @c_sdsp
sw110 . . . 10 @c_swsp
c_fswsp_sdsp 111 . . . 10 @c_fswsp_sdsp
#C.SDSP:RV64;C.FSWSP:RV32
Reviewed-by: Palmer Dabbelt
where rd=0 is illegal in the compressed ISA, but again we
don't appear to handle these correctly before the cleanups.
fld 001 . . . 10 @c_ldsp
lw010 . . . 10 @c_lwsp
c_flwsp_ldsp 011 . . . 10 @c_flwsp_ldsp
#C.LDSP:RV64;C.FLWSP:RV32
Reviewed-by: Palmer Dabbelt
t;, "s5", "s6", "s7",
+ "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
};
const char * const riscv_fpr_regnames[] = {
- "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ", "ft7 ",
- "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ", "fa5 ",
- "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ", "fs7 ",
- "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10", "ft11"
+ "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
+ "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
+ "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
+ "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
};
const char * const riscv_excp_names[] = {
Reviewed-by: Palmer Dabbelt
. 10 @c_mv
@@ -153,4 +125,3 @@ c_flwsp_ldsp 011 . . . 10 @c_flwsp_ldsp
#C.LDSP:RV64;C.FLWSP:RV32
}
fsd 101 .. . 10 @c_sdsp
sw110 . . . 10 @c_swsp
-c_fswsp_sdsp 111 . . . 10 @c_fswsp_sdsp
#C.SDSP:RV64;C.FSWSP:RV32
Reviewed-by: Palmer Dabbelt
RGET_DIR)$@)
target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
target/riscv/decode_insn16.inc.c
Reviewed-by: Palmer Dabbelt
..77f794ed70 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -34,9 +34,13 @@
%imm_u12:s20 !function=ex_shift_12
# Argument sets:
+
If I understand decodetree correctly, this isn't used until patch 5.
Otherwise,
Reviewed-by: Palmer Dabbelt
I
I actually missed this. I just added it to for-next on
github.com/palmer-dabbelt.
Thanks for the ping!
On Fri, 12 Apr 2019 14:23:42 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Apr 12, 2019 at 2:15 PM Jonathan Behrens wrote:
Just to double check, nothing further on this is need from
address starts at
an offset of 0x04 and not 0x00.
riscv: virt: Fix PLIC priority base offset
Update the virt offsets based on the newly updated SiFive U and SiFive E
offsets.
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c | 4 ++--
include/hw
From: Alistair Francis
Instead of using error_report() to print guest errors let's use
qemu_log_mask(LOG_GUEST_ERROR,...) to log the error.
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions
The following changes since commit 061b51e9195670e9d190cdec46fabcb3c77763fb:
Update version for v4.0.0-rc2 release (2019-04-02 17:01:20 +0100)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-rc3-v2
for you to fetch changes up
On Thu, 04 Apr 2019 11:18:52 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Apr 4, 2019 at 1:45 AM Peter Maydell wrote:
On Thu, 4 Apr 2019 at 08:00, Palmer Dabbelt wrote:
>
> The following changes since commit 49fc899f8d673dd9e73f3db0d9e9ea60b77c331b:
>
> Update version fo
The following changes since commit 49fc899f8d673dd9e73f3db0d9e9ea60b77c331b:
Update version for v4.0.0-rc1 release (2019-03-26 17:02:29 +)
are available in the Git repository at:
git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-rc3
for you to fetch changes up
On Wed, 03 Apr 2019 16:32:11 PDT (-0700), alistai...@gmail.com wrote:
On Wed, Mar 27, 2019 at 8:23 PM Palmer Dabbelt wrote:
On Wed, 27 Mar 2019 11:51:15 PDT (-0700), Alistair Francis wrote:
> This series updates the PLIC address to match the documentation.
>
> This fixes: https://g
address starts at
an offset of 0x04 and not 0x00.
riscv: virt: Fix PLIC priority base offset
Update the virt offsets based on the newly updated SiFive U and SiFive E
offsets.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_plic.c
From: Alistair Francis
Instead of using error_report() to print guest errors let's use
qemu_log_mask(LOG_GUEST_ERROR,...) to log the error.
Signed-off-by: Alistair Francis
Reviewed-by: Palmer Dabbelt
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Palmer Dabbelt
---
hw/riscv
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