On Fri, Jun 02, 2023 at 07:58:30PM -0700, Richard Henderson wrote:
> On 6/2/23 07:02, Andrew Jones wrote:
> > > +struct riscv_hwprobe {
> > > +int64_t key;
> > > +uint64_t value;
> > > +};
> >
> > The above is all uapi so Linux's ar
e_max,
> is_32_bit));
> +qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);
> +g_free(sv_name);
> +}
>
> name = riscv_isa_string(cpu_ptr);
> qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
> --
> 2.40.1
>
>
Adding a sentence, like what I wrote above, to the commit message in order
to provide better justification might be nice, but either way
Reviewed-by: Andrew Jones
Thanks,
drew
t; +
> static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -1841,6 +1866,10 @@ static void riscv_cpu_class_init(ObjectClass *c, void
> *data)
> cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
> cc->tcg_ops = &riscv_tcg_ops;
>
> +object_class_property_add(c, "mvendorid", "uint32", NULL,
> + cpu_set_mvendorid,
> + NULL, NULL);
> +
Shouldn't we provide a get function as well?
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> --
> 2.40.1
>
>
Otherwise,
Reviewed-by: Andrew Jones
cpu_set_mvendorid,
> NULL, NULL);
>
> +object_class_property_add(c, "mimpid", "uint64", NULL,
> + cpu_set_mimpid,
> + NULL, NULL);
> +
Same, shouldn't we also define 'get' comment as the last patch.
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> --
> 2.40.1
>
>
Reviewed-by: Andrew Jones
"
> + "and the remaining bits zero", mxlen);
> +return;
> +}
> +
> +cpu->cfg.marchid = value;
> +}
> +
> static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -1893,6 +1928,10 @@ static void riscv_cpu_class_init(ObjectClass *c, void
> *data)
>cpu_set_mimpid,
>NULL, NULL);
>
> +object_class_property_add(c, "marchid", "uint64", NULL,
> + cpu_set_marchid,
> + NULL, NULL);
> +
get?
> device_class_set_props(dc, riscv_cpu_properties);
> }
>
> --
> 2.40.1
>
>
Otherwise,
Reviewed-by: Andrew Jones
to
> init other KVM specific properties in the next patches as well.
>
> [1] target/arm/kvm.c, kvm_arm_create_scratch_host_vcpu()
>
> Suggested-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 4 ++
> target/riscv/kvm.c | 85 ++++
> target/riscv/kvm_riscv.h | 1 +
> 3 files changed, 90 insertions(+)
>
Reviewed-by: Andrew Jones
KVM_REG_RISCV_CONFIG_REG(mimpid));
> +reg.addr = (uint64_t)&cpu->cfg.mimpid;
> +ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®);
> +if (ret != 0) {
> + error_report("Unable to retrieve mimpid from host, error %d", ret);
> +}
> }
>
> void kvm_riscv_init_user_properties(Object *cpu_obj)
> --
> 2.40.1
>
>
Reviewed-by: Andrew Jones
rch_init_vcpu(CPUState *cs)
> }
> env->misa_ext = isa;
>
> +if (!object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST)) {
> +ret = kvm_vcpu_set_machine_ids(cpu, cs);
> +}
> +
> return ret;
> }
>
> --
> 2.40.1
>
>
Reviewed-by: Andrew Jones
34 +++---
> 1 file changed, 23 insertions(+), 11 deletions(-)
>
Reviewed-by: Andrew Jones
On Tue, May 30, 2023 at 04:46:18PM -0300, Daniel Henrique Barboza wrote:
> Using all TCG user properties in KVM is tricky. First because KVM
> supports only a small subset of what TCG provides, so most of the
> cpu->cfg flags do nothing for KVM.
>
> Second, and more important, we don't have a way
On Tue, May 30, 2023 at 04:46:20PM -0300, Daniel Henrique Barboza wrote:
> Let's add KVM user properties for the multi-letter extensions that KVM
> currently supports: zicbom, zicboz, zihintpause, zbb, ssaia, sstc,
> svinval and svpbmt.
>
> As with the recently added MISA properties we're also goi
On Tue, May 30, 2023 at 04:46:19PM -0300, Daniel Henrique Barboza wrote:
> Our design philosophy with KVM properties can be resumed in two main
> decisions based on KVM interface availability and what the user wants to
> do:
>
> - if the user disables an extension that the host KVM module doesn't
On Tue, May 30, 2023 at 04:46:21PM -0300, Daniel Henrique Barboza wrote:
> KVM is not using the same attributes as TCG, i.e. it doesn't use
> isa_edata_arr[]. Add a new kvm_riscv_isa_string_ext() helper that does
> basically the same thing, but using KVM internals instead.
>
> The decision to add
, ret);
> +exit(EXIT_FAILURE);
> +}
> +}
> +}
> +
> static void kvm_riscv_add_cpu_user_properties(Object *cpu_obj)
> {
> int i;
> @@ -829,6 +855,7 @@ int kvm_arch_init_vcpu(CPUState *cs)
> }
>
> kvm_riscv_update_cpu_misa_ext(cpu, cs);
> +kvm_riscv_update_cpu_cfg_isa_ext(cpu, cs);
>
> return ret;
> }
> --
> 2.40.1
>
>
Reviewed-by: Andrew Jones
On Tue, May 30, 2023 at 04:46:23PM -0300, Daniel Henrique Barboza wrote:
> If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the
> Linux Kernel will fail to detect the availability of the CBOM/CBOZ
> extensions, regardless of the contents of the 'riscv,isa' DT prop.
>
> The FDT is
On Wed, Jun 07, 2023 at 04:59:02PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 6/7/23 08:48, Andrew Jones wrote:
> > On Tue, May 30, 2023 at 04:46:20PM -0300, Daniel Henrique Barboza wrote:
> > > Let's add KVM user properties for the multi-letter extensions that
On Wed, Jun 07, 2023 at 05:37:16PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 6/7/23 10:01, Andrew Jones wrote:
> > On Tue, May 30, 2023 at 04:46:23PM -0300, Daniel Henrique Barboza wrote:
> > > If we don't set a proper cbom_blocksize|cboz_blocksize in the FD
On Thu, Jun 08, 2023 at 12:23:10AM -0700, Tommy Wu wrote:
> This patchset added support for Smrnmi Extension in RISC-V.
>
> There are four new CSRs and one new instruction added to allow NMI to be
> resumable in RISC-V, which are:
>
> =
Please add a commit message to all patches of the series.
Another comment below.
On Thu, Jun 08, 2023 at 12:23:11AM -0700, Tommy Wu wrote:
> Signed-off-by: Frank Chang
> Signed-off-by: Tommy Wu
> ---
> hw/riscv/riscv_hart.c | 21 +
> include/hw/riscv/riscv_hart.h
could be shared. Additionally, other
approaches to creating sysroots, such as with debootstrap, may be
documented in this file in the future.
Signed-off-by: Andrew Jones
---
docs/devel/cross-compiling.rst | 221 +
docs/devel/index-build.rst | 1 +
2 files ch
On Thu, Sep 07, 2023 at 01:13:33PM +1000, Alistair Francis wrote:
> On Wed, Jul 26, 2023 at 10:08 PM Andrew Jones wrote:
> >
> > Add instructions for how to cross-compile QEMU for RISC-V. The
> > file is named generically because there's no reason not to collect
> >
On Thu, Sep 07, 2023 at 11:20:55AM +0100, Alex Bennée wrote:
>
> Andrew Jones writes:
>
> > Add instructions for how to cross-compile QEMU for RISC-V. The
> > file is named generically because there's no reason not to collect
> > other architectures steps into t
On Thu, Sep 07, 2023 at 02:31:20PM +0200, Andrew Jones wrote:
> On Thu, Sep 07, 2023 at 11:20:55AM +0100, Alex Bennée wrote:
> >
> > Andrew Jones writes:
> >
> > > Add instructions for how to cross-compile QEMU for RISC-V. The
> > > file is named gener
TIMER_CNT register to restore trapless ptimer
> > access.
> >
> > Quoting Andrew Jones:
> >
> > Simply reading the CNT register and writing back the same value is
> > enough to set an offset, since the timer will have certainly moved
> > past whatever valu
obj, Visitor *v, const char *name,
>void *opaque, Error **errp)
> {
> @@ -2011,6 +2032,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .instance_size = sizeof(RISCVCPU),
> .instance_align = __alignof__(RISCVCPU),
> .instance_init = riscv_cpu_init,
> +.instance_post_init = riscv_cpu_post_init,
> .abstract = true,
> .class_size = sizeof(RISCVCPUClass),
> .class_init = riscv_cpu_class_init,
> --
> 2.41.0
>
Reviewed-by: Andrew Jones
c01374f..ef6b2cfffe 100644
> --- a/target/riscv/kvm.c
> +++ b/target/riscv/kvm.c
> @@ -1279,6 +1279,7 @@ void kvm_riscv_cpu_add_kvm_properties(Object *obj)
> DeviceState *dev = DEVICE(obj);
>
> riscv_init_user_properties(obj);
> + riscv_add_satp_mode_properties(obj);
> riscv_cpu_add_misa_properties(obj);
>
> riscv_cpu_add_kvm_unavail_prop_array(obj, riscv_cpu_extensions);
> --
> 2.41.0
>
Reviewed-by: Andrew Jones
On Wed, Sep 06, 2023 at 12:23:19PM +0200, Philippe Mathieu-Daudé wrote:
> On 6/9/23 11:16, Daniel Henrique Barboza wrote:
> > This file is not needed for some time now. All the stubs implemented in
> > it (kvm_riscv_reset_vcpu() and kvm_riscv_set_irq()) are wrapped in 'if
> > kvm_enabled()' blocks
FIG_KVM
> -void kvm_riscv_cpu_add_kvm_properties(Object *obj);
> void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
> void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
> void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift,
> @@ -29,11 +28,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t
> group_shift,
>uint64_t guest_num);
> void riscv_kvm_aplic_request(void *opaque, int irq, int level);
> #else
> -static inline void kvm_riscv_cpu_add_kvm_properties(Object *obj)
> -{
> -g_assert_not_reached();
> -}
> -
> static inline void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
> {
> g_assert_not_reached();
> --
> 2.41.0
>
Reviewed-by: Andrew Jones
off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 34 ++
> target/riscv/cpu.h | 1 +
> 2 files changed, 19 insertions(+), 16 deletions(-)
>
Reviewed-by: Andrew Jones
misa_cfg->description);
> - object_property_set_bool(cpu_obj, misa_cfg->name,
> - misa_cfg->enabled, NULL);
> +object_property_set_description(cpu_obj, name, desc);
> +object_property_set_bool(cpu_obj, name, misa_cfg->enabled, NULL);
> }
> }
>
> --
> 2.41.0
>
Reviewed-by: Andrew Jones
On Mon, Sep 11, 2023 at 09:49:06AM +0200, Andrew Jones wrote:
> On Wed, Sep 06, 2023 at 12:23:19PM +0200, Philippe Mathieu-Daudé wrote:
> > On 6/9/23 11:16, Daniel Henrique Barboza wrote:
> > > This file is not needed for some time now. All the stubs implemented in
> > &g
On Tue, Sep 12, 2023 at 09:05:41AM +0300, Michael Tokarev wrote:
> 12.09.2023 00:43, Daniel Henrique Barboza:
> > On 9/11/23 16:54, Michael Tokarev wrote:
> ...
> > > > /* KVM AIA only has one APLIC instance */
> > > > - if (virt_use_kvm_aia(s)) {
> > > > + if (kvm_enabled() && virt_use
On Fri, Oct 20, 2023 at 07:39:48PM -0300, Daniel Henrique Barboza wrote:
> The TCG emulation implements all the extensions described in the
> RVA22U64 profile, both mandatory and optional. The mandatory extensions
> will be enabled via the profile flag. We'll leave the optional
> extensions to be e
WRITE));
> -aml_append(dev, aml_name_decl("_CRS", crs));
> -aml_append(scope, dev);
> -}
> -
> /* RHCT Node[N] starts at offset 56 */
> #define RHCT_NODE_ARRAY_OFFSET 56
>
> @@ -226,7 +211,7 @@ static void build_dsdt(GArray *table_data,
> scope = aml_scope("\\_SB");
> acpi_dsdt_add_cpus(scope, s);
>
> -acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
> +fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]);
>
> aml_append(dsdt, scope);
>
> diff --git a/include/hw/nvram/fw_cfg_acpi.h b/include/hw/nvram/fw_cfg_acpi.h
> new file mode 100644
> index 00..6e2c5f04b7
> --- /dev/null
> +++ b/include/hw/nvram/fw_cfg_acpi.h
> @@ -0,0 +1,9 @@
And an SPDX here too.
> +#ifndef FW_CFG_ACPI_H
> +#define FW_CFG_ACPI_H
> +
> +#include "qemu/osdep.h"
> +#include "exec/hwaddr.h"
> +
> +void fw_cfg_acpi_dsdt_add(Aml *scope, const MemMapEntry *fw_cfg_memmap);
> +
> +#endif
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones
> + aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
> + AML_EXCLUSIVE, &irq, 1));
> +aml_append(dev, aml_name_decl("_CRS", crs));
> +aml_append(scope, dev);
> +base += size;
> +}
> +}
> diff --git a/include/hw/virtio/virtio-acpi.h b/include/hw/virtio/virtio-acpi.h
> new file mode 100644
> index 00..b8687b1b42
> --- /dev/null
> +++ b/include/hw/virtio/virtio-acpi.h
> @@ -0,0 +1,11 @@
> +#ifndef VIRTIO_ACPI_H
> +#define VIRTIO_ACPI_H
> +
> +#include "qemu/osdep.h"
> +#include "exec/hwaddr.h"
> +
> +void virtio_acpi_dsdt_add(Aml *scope, const MemMapEntry *virtio_mmio_memmap,
> + uint32_t mmio_irq, int num);
> +
> +#endif
> +
> --
> 2.34.1
>
Shouldn't we also try to apply this to microvm which has nearly the same
code?
Otherwise,
Reviewed-by: Andrew Jones
iewed-by: Alistair Francis
> ---
> hw/riscv/virt.c | 25 +
> include/hw/riscv/virt.h | 25 +
> 2 files changed, 26 insertions(+), 24 deletions(-)
>
Reviewed-by: Andrew Jones
hanged, 34 insertions(+)
>
Reviewed-by: Andrew Jones
; hw/riscv/virt-acpi-build.c | 36 ++--
> 1 file changed, 34 insertions(+), 2 deletions(-)
>
Reviewed-by: Andrew Jones
t;
> Signed-off-by: Sunil V L
> Reviewed-by: Daniel Henrique Barboza
> ---
> hw/riscv/virt-acpi-build.c | 64 +-
> 1 file changed, 56 insertions(+), 8 deletions(-)
>
Reviewed-by: Andrew Jones
On Thu, Oct 19, 2023 at 06:56:44PM +0530, Sunil V L wrote:
> MMU type information is available via MMU node in RHCT. Add this node in
> RHCT.
>
> Signed-off-by: Sunil V L
> Reviewed-by: Daniel Henrique Barboza
> ---
> hw/riscv/virt-acpi-build.c | 36
> 1 fil
On Thu, Oct 19, 2023 at 06:56:43PM +0530, Sunil V L wrote:
> When CMO related extensions like Zicboz, Zicbom and Zicbop are enabled, the
> block size for those extensions need to be communicated via CMO node in
> RHCT. Add CMO node in RHCT if any of those CMO extensions are detected.
>
> Signed-of
build_append_int_noprefix(table_data, s->memmap[VIRT_PLIC].size,
> 4);
> +/* PLIC Address */
> +build_append_int_noprefix(table_data, aplic_addr, 8);
> +/* Global System Interrupt Vector Base */
> +build_append_int_noprefix(table_data, gsi_base, 4);
> +}
> }
>
> acpi_table_end(linker, &table);
> --
> 2.34.1
>
Otherwise,
Reviewed-by: Andrew Jones
On Mon, Oct 23, 2023 at 02:00:00PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 10/23/23 05:16, Andrew Jones wrote:
> > On Fri, Oct 20, 2023 at 07:39:48PM -0300, Daniel Henrique Barboza wrote:
> > > The TCG emulation implements all the extensions described in the
>
On Wed, Oct 25, 2023 at 10:49:53AM -0300, Daniel Henrique Barboza wrote:
> The rva22U64 profile, described in:
>
> https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles
>
> Contains a set of CPU extensions aimed for 64-bit userspace
> applications. Enabling this set to be
riscv_cpu_vendor_exts);
> riscv_cpu_add_kvm_unavail_prop_array(cpu_obj,
> riscv_cpu_experimental_exts);
> +
> + /* We don't have the needed KVM support for profiles */
> +for (i = 0; riscv_profiles[i] != NULL; i++) {
> +riscv_cpu_add_kvm_unavail_prop(cpu_obj, riscv_profiles[i]->name);
> +}
> }
>
> static int kvm_riscv_get_regs_core(CPUState *cs)
> --
> 2.41.0
>
>
Reviewed-by: Andrew Jones
erty_add(cpu_obj, profile->name, "bool",
> +cpu_get_profile, cpu_set_profile,
> +NULL, (void *)profile);
> +}
> +}
> +
> static bool cpu_ext_is_deprecated(const char *ext_name)
> {
> return isupper(ext_name[0]);
> @@ -892,6 +943,8 @@ static void riscv_cpu_add_user_properties(Object *obj)
>
> riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts);
>
> +riscv_cpu_add_profiles(obj);
> +
> for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {
> qdev_property_add_static(DEVICE(obj), prop);
> }
> --
> 2.41.0
>
>
Reviewed-by: Andrew Jones
IU Zhiwei
> ---
> target/riscv/tcg/tcg-cpu.c | 15 ++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
Reviewed-by: Andrew Jones
tion.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Alistair Francis
> Reviewed-by: LIU Zhiwei
> ---
> target/riscv/tcg/tcg-cpu.c | 44 --
> 1 file changed, 23 insertions(+), 21 deletions(-)
>
Reviewed-by: Andrew Jones
t; +}
> +
> for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) {
> ext_offset = profile->ext_offsets[i];
>
> --
> 2.41.0
>
>
Reviewed-by: Andrew Jones
tcg/tcg-cpu.c | 28
> 1 file changed, 16 insertions(+), 12 deletions(-)
>
Reviewed-by: Andrew Jones
ser set and priv version will never fail for these
> extensions, making cpu_cfg_ext_auto_update() redundant.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/tcg/tcg-cpu.c | 73 +-
> 1 file changed, 48 insertions(+), 25 deletions(-)
>
Reviewed-by: Andrew Jones
---
> target/riscv/tcg/tcg-cpu.c | 57 ++++++
> 1 file changed, 57 insertions(+)
>
Reviewed-by: Andrew Jones
generic CPUs are already set to priv_ver
> LATEST.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: Andrew Jones
> ---
> target/riscv/tcg/tcg-cpu.c | 32
> 1 file changed, 32 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg
ing rva22u64 using the following options:
>
> -cpu rv64i,rva22u64=true,sv39=true,g=true,c=true,s=true
>
> Note that being an usermode/application profile we still need to
> explicitly set 's=true' to enable Supervisor mode to boot Linux.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/tcg/tcg-cpu.c | 80 ++
> 1 file changed, 80 insertions(+)
>
Reviewed-by: Andrew Jones
riscv_cpu_validate_zic64b too). We should probably double check all
our uses of that word in function names. This function, for example,
doesn't check ("validate") anything it just does an assignment ("set"), so
riscv_cpu_set_svade() would seem more appropriate. (And, we don't really
even need the function, IMO).
> +{
> +cpu->cfg.svade = !cpu->cfg.ext_svadu;
> +}
> +
> static void riscv_cpu_validate_named_features(RISCVCPU *cpu)
> {
> +riscv_cpu_validate_svade(cpu);
> riscv_cpu_validate_zic64b(cpu);
> }
>
> --
> 2.41.0
>
Otherwise,
Reviewed-by: Andrew Jones
On Thu, Nov 23, 2023 at 04:15:27PM -0300, Daniel Henrique Barboza wrote:
> Some profiles, like RVA22S64, has a priv_spec requirement.
>
> Make this requirement explicit for all profiles. We'll validate this
> requirement finalize() time and, in case the user chooses an
> incompatible priv_spec whi
On Thu, Nov 23, 2023 at 07:12:59PM +0100, Christoph Muellner wrote:
> From: Christoph Müllner
>
> Upstream Linux recently added RISC-V Zicboz support to the hwprobe API.
> This patch introduces this for QEMU's user space emulator.
>
> Signed-off-by: Christoph Müllner
> ---
> linux-user/syscall
-error_propagate(errp, local_err);
> -return;
> -}
> -#endif
Assuming we'll be getting KVM's supported mode with
KVM_REG_RISCV_CONFIG_REG(satp_mode) prior to calling
riscv_cpu_finalize_features(), then this looks good to me.
Reviewed-by: Andrew Jones
Thanks,
drew
gt;enabled = value;
>
> +
stray blank line
> if (profile->enabled) {
> cpu->env.priv_ver = profile->priv_spec;
> }
>
> +#ifndef CONFIG_USER_ONLY
> +if (profile->satp_mode != RISCV_PROFILE_ATTR_UNUSED) {
> +const char *satp_prop = satp_mode_str(profile->satp_mode,
> + riscv_cpu_is_32bit(cpu));
> +object_property_set_bool(obj, satp_prop, profile->enabled, NULL);
> +}
> +#endif
> +
> for (i = 0; misa_bits[i] != 0; i++) {
> uint32_t bit = misa_bits[i];
>
> --
> 2.41.0
>
Otherwise
Reviewed-by: Andrew Jones
ILE_EXT_LIST_END
> +}
> +};
> +
> RISCVCPUProfile *riscv_profiles[] = {
> &RVA22U64,
> +&RVA22S64,
> NULL,
> };
>
> --
> 2.41.0
>
Since S-mode profiles will all presumably state they support everything a
U-mode profile supports too, then I wonder if we shouldn't be able to
point S-mode profiles at U-mode profiles somehow, rather than redundantly
add their extensions.
Anyway,
Reviewed-by: Andrew Jones
Thanks,
drew
@@ -1975,6 +1982,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
> DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init),
> DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init),
> +DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init),
> #endif
> };
>
> --
> 2.41.0
>
Reviewed-by: Andrew Jones
_cpu_is_32bit(RISCVCPU *cpu);
>
> RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
> target_ulong *ret_value,
> --
> 2.41.0
>
Reviewed-by: Andrew Jones
On Fri, Nov 24, 2023 at 06:41:25PM +0100, Christoph Müllner wrote:
> On Fri, Nov 24, 2023 at 5:59 PM Andrew Jones wrote:
> >
> > On Thu, Nov 23, 2023 at 07:12:59PM +0100, Christoph Muellner wrote:
> > > From: Christoph Müllner
> > >
> > > Upstream Lin
les changed, 34 insertions(+)
>
Reviewed-by: Andrew Jones
'parent' to consider the possibility of other
> uses (e.g. a s-mode profile including a previous s-mode profile) in the
> future.
>
> Suggested-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cp
enabled:
>
> # cat /proc/cpuinfo
> processor : 0
> hart : 0
> isa :
> rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihintpause_zihpm_zfhmin_zca_zcd_zba_zbb_zbs_zkt_svinval_svpbmt
> mmu : sv39
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 32
> 1 file changed, 32 insertions(+)
>
Reviewed-by: Andrew Jones
On Tue, Jan 02, 2024 at 08:40:48AM -0300, Daniel Henrique Barboza wrote:
> Hi,
>
> Drew brought to my attention the following post on the tech-unprivileged
> mailing
> list:
>
> "Architecture Review Committee meeting minutes, 12/19/23"
> https://lists.riscv.org/g/tech-unprivileged/message/611
>
char, maxlen);
> +g_autofree char *riscv_isa;
> +char **isa_extensions;
> +int count = 0;
> +
> +riscv_isa = riscv_isa_string(cpu);
> +qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", riscv_isa);
> +
> +snprintf(isa_base, maxlen, "rv%d
On Mon, Dec 18, 2023 at 02:37:55PM +1000, Alistair Francis wrote:
...
> > +void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> > +{
> > +const size_t maxlen = sizeof("rv128i");
> > +g_autofree char *isa_base = g_new(char, maxlen);
> > +g_autofree char *riscv_isa;
> > +
On Wed, Jan 10, 2024 at 10:25:36AM +, Conor Dooley wrote:
> From: Conor Dooley
>
> A cpu may not have the same xlen as the compile time target, and
> misa_mxl_max is the source of truth for what the hart supports.
>
> Reported-by: Andrew Jones
> Link:
> https://lo
en = 16 << cpu->env.misa_mxl_max;
> +
> +riscv_isa = riscv_isa_string(cpu);
> +qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", riscv_isa);
> +
> +snprintf(isa_base, maxlen, "rv%di", xlen);
> +qemu_fdt_setprop_string(fdt, nodename, "riscv,isa-base", isa_base);
> +
> +isa_extensions = riscv_isa_extensions_list(cpu, &count);
> +qemu_fdt_setprop_string_array(fdt, nodename, "riscv,isa-extensions",
> + isa_extensions, count);
> +
> +for (int i = 0; i < count; i++) {
> +g_free(isa_extensions[i]);
> +}
> +
> +g_free(isa_extensions);
> +}
> +#endif
> +
> #define DEFINE_CPU(type_name, initfn) \
> { \
> .name = type_name, \
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 5f3955c38d..192d0c2d31 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -510,6 +510,7 @@ char *riscv_isa_string(RISCVCPU *cpu);
> #define cpu_mmu_index riscv_cpu_mmu_index
>
> #ifndef CONFIG_USER_ONLY
> +void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename);
> void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> vaddr addr, unsigned size,
> MMUAccessType access_type,
> --
> 2.39.2
>
Reviewed-by: Andrew Jones
On Wed, Jan 10, 2024 at 03:32:21PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 1/9/24 14:07, Rob Bradford wrote:
> > Signed-off-by: Rob Bradford
> > ---
> > target/riscv/tcg/tcg-cpu.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/tcg/tcg-cpu
On Tue, Jan 09, 2024 at 05:07:35PM +, Rob Bradford wrote:
> Add the infrastructure for the 'B' extension which is the union of the
> Zba, Zbb and Zbs instructions.
>
> Signed-off-by: Rob Bradford
> ---
> target/riscv/cpu.c | 5 +++--
> target/riscv/cpu.h | 1 +
> target/riscv
cy between chosen extensions while setting
> * cpu->cfg accordingly.
> @@ -309,6 +338,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
> env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
> }
>
> +if (riscv_has_ext(env, RVB)) {
> +riscv_cpu_validate_b(cpu);
> +}
> +
> if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
> error_setg(errp,
> "I and E extensions are incompatible");
> --
> 2.43.0
>
>
Reviewed-by: Andrew Jones
On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote:
> On Tue, Jan 09, 2024 at 05:07:35PM +, Rob Bradford wrote:
> > Add the infrastructure for the 'B' extension which is the union of the
> > Zba, Zbb and Zbs instructions.
> >
> > Signed-off-
it a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 8a35683a34..fda54671d5 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -791,6 +791,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> MISA_CFG(RVJ, false),
> MISA_CFG(RVV, false),
> MISA_CFG(RVG, false),
> +MISA_CFG(RVB, false)
> };
>
> /*
> --
> 2.43.0
>
>
Reviewed-by: Andrew Jones
On Thu, Jan 11, 2024 at 03:17:25PM +, Rob Bradford wrote:
> + Ved
>
> On Thu, 2024-01-11 at 14:14 +0100, Andrew Jones wrote:
> > On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote:
> > > On Tue, Jan 09, 2024 at 05:07:35PM +, Rob Bradford wrote:
> >
no one noticed
> this is because we're not implementing kvm_cpu_synchronize_state() in
> RISC-V yet.
>
> Create a new helper that returns a KVM ID with u32 size and use it in
> RISCV_FP_F_REG().
>
> Reported-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboz
ns a KVM ID with u64 size and use it with
> RISCV_FP_D_REG().
>
> Reported-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm/kvm-cpu.c | 11 ---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/kvm
_TIMER_REG() to fix it.
>
> Reported-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm/kvm-cpu.c | 26 +-
> 1 file changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/risc
= kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
> - KVM_REG_RISCV_CONFIG_REG(marchid));
> +id = RISCV_CONFIG_REG(env, marchid);
> ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid);
> if (ret != 0) {
> return ret;
> }
>
> -id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
> - KVM_REG_RISCV_CONFIG_REG(mimpid));
> +id = RISCV_CONFIG_REG(env, mimpid);
> ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid);
>
> return ret;
> --
> 2.41.0
>
Reviewed-by: Andrew Jones
or (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
> multi_ext_cfg = &kvm_multi_ext_cfgs[i];
> -reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT,
> - multi_ext_cfg->kvm_reg_id);
> +reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT,
> +multi_ext_cfg->kvm_reg_id);
> reg_search = bsearch(®_id, reglist->reg, reglist->n,
> sizeof(uint64_t), uint64_cmp);
> if (!reg_search) {
> --
> 2.41.0
>
Reviewed-by: Andrew Jones
On Mon, Oct 16, 2023 at 03:39:40PM +1000, Alistair Francis wrote:
> On Fri, Aug 11, 2023 at 5:01 PM Andrew Jones wrote:
> >
> > On Thu, Aug 10, 2023 at 02:07:17PM -0400, Alistair Francis wrote:
> > > On Tue, Aug 8, 2023 at 6:10 PM Vineet Gupta wrote:
> > > >
On Thu, Oct 12, 2023 at 04:07:50PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 10/11/23 00:01, Alistair Francis wrote:
> > On Sat, Oct 7, 2023 at 12:23 AM Daniel Henrique Barboza
> > wrote:
> > >
> > > Hi,
> > >
> > > Several design changes were made in this version after the reviews and
>
On Tue, Oct 17, 2023 at 01:55:47PM +1000, Alistair Francis wrote:
> On Mon, Oct 16, 2023 at 7:03 PM Andrew Jones wrote:
> >
> > On Thu, Oct 12, 2023 at 04:07:50PM -0300, Daniel Henrique Barboza wrote:
> > >
> > >
> > > On 10/11/23 00:01, Alistair Franci
On Thu, Oct 26, 2023 at 01:37:01AM +0530, Sunil V L wrote:
...
> diff --git a/hw/nvram/fw_cfg-acpi.c b/hw/nvram/fw_cfg-acpi.c
> new file mode 100644
> index 00..eddaffc09b
> --- /dev/null
> +++ b/hw/nvram/fw_cfg-acpi.c
> @@ -0,0 +1,44 @@
> +/*
> + * Add fw_cfg device in DSDT
> + *
> + * Cop
he MMU
node is now getting generated after the CMO node, so moving this up
means the offsets are still not in ascending order.
> if (cmo_offset) {
> build_append_int_noprefix(table_data, cmo_offset, 4);
> }
> +
> }
>
> acpi_table_end(linker, &table);
> --
> 2.39.2
>
>
Anyway,
Reviewed-by: Andrew Jones
Thanks,
drew
ic_socket_addr +
> + local_cpu_id * IMSIC_HART_SIZE(guest_index_bits);
> +imsic_size = IMSIC_HART_SIZE(guest_index_bits);
> +riscv_acpi_madt_add_rintc(i, local_cpu_id, arch_ids, table_data,
> + s->aia_type, imsic_addr, imsic_size);
All the above new lines identically match the new lines in
acpi_dsdt_add_cpus(), so I suggest creating a helper function rather
than duplicating them.
> }
>
> acpi_table_end(linker, &table);
> --
> 2.39.2
>
>
Otherwise,
Reviewed-by: Andrew Jones
Thanks,
drew
On Wed, Oct 25, 2023 at 08:44:50PM -0300, Daniel Henrique Barboza wrote:
> zic64b is defined in the RVA22U64 profile [1] as a named feature for
> "Cache blocks must be 64 bytes in size, naturally aligned in the address
> space". It's a fantasy name for 64 bytes cache blocks. RVA22U64
> mandates th
t; +++ b/target/riscv/cpu.h
> @@ -68,6 +68,18 @@ const char *riscv_get_misa_ext_description(uint32_t bit);
>
> #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
>
> +typedef struct riscv_cpu_profile {
> +const char *name;
> +uint32_t misa_ext;
> +bool enabled;
> +bool user_set;
> +const int32_t ext_offsets[];
> +} RISCVCPUProfile;
> +
> +#define RISCV_PROFILE_EXT_LIST_END -1
> +
> +extern RISCVCPUProfile *riscv_profiles[];
> +
> /* Privileged specification version */
> enum {
> PRIV_VERSION_1_10_0 = 0,
> --
> 2.41.0
>
Other than the nits and my wishy-washy-ness on the synthetic extensions,
Reviewed-by: Andrew Jones
Thanks,
drew
On Wed, Oct 25, 2023 at 08:44:50PM -0300, Daniel Henrique Barboza wrote:
> zic64b is defined in the RVA22U64 profile [1] as a named feature for
> "Cache blocks must be 64 bytes in size, naturally aligned in the address
> space". It's a fantasy name for 64 bytes cache blocks. RVA22U64
> mandates th
On Thu, Oct 26, 2023 at 07:36:21AM -0700, Andrea Bolognani wrote:
> On Mon, Oct 23, 2023 at 07:35:16PM +0200, Andrew Jones wrote:
> > On Mon, Oct 23, 2023 at 02:00:00PM -0300, Daniel Henrique Barboza wrote:
> > > On 10/23/23 05:16, Andrew Jones wrote:
> > > > Hmm, I&#
On Fri, Oct 27, 2023 at 02:52:38PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 10/26/23 14:36, Andrea Bolognani wrote:
> > On Thu, Oct 26, 2023 at 05:14:49PM +0200, Andrew Jones wrote:
> > > On Thu, Oct 26, 2023 at 07:36:21AM -0700, Andrea Bolognani wrote:
> >
g.h
> @@ -65,6 +65,7 @@ struct RISCVCPUConfig {
> bool ext_zicntr;
> bool ext_zicsr;
> bool ext_zicbom;
> +bool ext_zicbop;
> bool ext_zicboz;
> bool ext_zicond;
> bool ext_zihintntl;
> @@ -134,6 +135,7 @@ struct RISCVCPUConfig {
> uint16_t vlen;
> uint16_t elen;
> uint16_t cbom_blocksize;
> +uint16_t cbop_blocksize;
> uint16_t cboz_blocksize;
> bool mmu;
> bool pmp;
> --
> 2.41.0
>
Otherwise,
Reviewed-by: Andrew Jones
Thanks,
drew
On Sat, Oct 28, 2023 at 05:54:17AM -0300, Daniel Henrique Barboza wrote:
> zic64b is defined in the RVA22U64 profile [1] as a named feature for
> "Cache blocks must be 64 bytes in size, naturally aligned in the address
> space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64
> profile
object_unref(obj);
> +return NULL;
> +}
> +
> expansion_info = g_new0(CpuModelExpansionInfo, 1);
> expansion_info->model = g_malloc0(sizeof(*expansion_info->model));
> expansion_info->model->name = g_strdup(model->name);
> @@ -200,6 +219,7 @@ CpuModelExpansionInfo
> *qmp_query_cpu_model_expansion(CpuModelExpansionType type,
> riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_extensions);
> riscv_obj_add_multiext_props(obj, qdict_out,
> riscv_cpu_experimental_exts);
> riscv_obj_add_multiext_props(obj, qdict_out, riscv_cpu_vendor_exts);
> +riscv_obj_add_named_feats_qdict(obj, qdict_out);
>
> /* Add our CPU boolean options too */
> riscv_obj_add_qdict_prop(obj, qdict_out, "mmu");
> --
> 2.41.0
>
Reviewed-by: Andrew Jones
On Sat, Oct 28, 2023 at 05:54:21AM -0300, Daniel Henrique Barboza wrote:
> The TCG emulation implements all the extensions described in the
> RVA22U64 profile, both mandatory and optional. The mandatory extensions
> will be enabled via the profile flag. We'll leave the optional
> extensions to be e
On Tue, Oct 31, 2023 at 05:39:03PM -0300, Daniel Henrique Barboza wrote:
> We don't have any form of a 'bare bones' CPU. rv64, our default CPUs,
> comes with a lot of defaults. This is fine for most regular uses but
> it's not suitable when more control of what is actually loaded in the
> CPU is re
on (e.g. throw a warning).
>
> [1]
> https://github.com/riscv/riscv-profiles/releases/download/v1.0/profiles.pdf
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 6 ++
> target/riscv/cpu.h | 1 +
> target/riscv/cpu_cfg.h | 1 +
> target/riscv/tcg/tcg-cpu.c | 14 ++
> 4 files changed, 22 insertions(+)
>
Reviewed-by: Andrew Jones
!= NULL; i++) {
> +riscv_cpu_validate_profile(cpu, riscv_profiles[i]);
> +}
> +}
> +
> void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
> {
> CPURISCVState *env = &cpu->env;
> @@ -649,6 +718,7 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error
> **errp)
> }
>
> riscv_cpu_validate_named_features(cpu);
> +riscv_cpu_validate_profiles(cpu);
>
> if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) {
> /*
> --
> 2.41.0
>
Other than the nits,
Reviewed-by: Andrew Jones
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