Re: [PATCH 02/17] bsp/arm: Separate setup for translation table

On 2014-02-27 08:44, Joel Sherrill wrote: On Feb 27, 2014 8:36 AM, Chris Johns wrote: > > On 27/02/2014 6:19 pm, Sebastian Huber wrote: > > On 2014-02-27 07:15, Ralf Corsepius wrote: > >> On 02/26/2014 08:03 PM, Gedare Bloom wrote: > >>> Perhaps the function should be split in two: > >>> a

Re: TCP/IP update, possible SMP (GSOC 2014)

Sebastian needs to update that page. On Feb 27, 2014 6:08 AM, Daniel Ramirez wrote: > > Hey all! > > I'm a student looking to participate with RTEMS for this year's summer of > code. I'm trying to flesh out some good project ideas. > > I was wondering about the current state of the TCP/IP update,

Re: [PATCH 02/17] bsp/arm: Separate setup for translation table

On Feb 27, 2014 8:36 AM, Chris Johns wrote: > > On 27/02/2014 6:19 pm, Sebastian Huber wrote: > > On 2014-02-27 07:15, Ralf Corsepius wrote: > >> On 02/26/2014 08:03 PM, Gedare Bloom wrote: > >>> Perhaps the function should be split in two: > >>> arm_cp15_setup_translation_table() > >> > >> I for

Re: [PATCH 02/17] bsp/arm: Separate setup for translation table

On 27/02/2014 6:19 pm, Sebastian Huber wrote: On 2014-02-27 07:15, Ralf Corsepius wrote: On 02/26/2014 08:03 PM, Gedare Bloom wrote: Perhaps the function should be split in two: arm_cp15_setup_translation_table() I for one, do find this function's name insufficiently descriptive/self-explanat

Re: [PATCH 04/17] bsp/arm: Add linker symbol bsp_processor_count

On 26/02/2014 9:51 pm, Ralf Kirchner wrote: --- c/src/lib/libbsp/arm/shared/include/linker-symbols.h |2 ++ 1 Datei geändert, 2 Zeilen hinzugefügt(+) diff --git a/c/src/lib/libbsp/arm/shared/include/linker-symbols.h b/c/src/lib/libbsp/arm/shared/include/linker-symbols.h index 6555e04..a8

Re: [PATCH 02/17] bsp/arm: Separate setup for translation table

On 2014-02-27 07:15, Ralf Corsepius wrote: On 02/26/2014 08:03 PM, Gedare Bloom wrote: Perhaps the function should be split in two: arm_cp15_setup_translation_table() I for one, do find this function's name insufficiently descriptive/self-explanatory. What kind of translation does it perform?

Re: [PATCH 1/8] sptests/spcache01: Detect write-through cache

On 2014-02-26 20:25, Gedare Bloom wrote: The logic here is that a write-through cache will have written back the lines in vdata, whereas a write-back cache won't since there are no cache conflicts before the invalidation. Did you run this test on a write-through target to verify it works as expec

Re: [PATCH 6/8] bsp/leon3: Add L2C registers

On 2014-02-26 20:33, Gedare Bloom wrote: Maybe it is just me, but l2c looks very close to i2c which might cause some confusion. The name is from the GRLIB manual, using something else might cause some confusion ;-) -- Sebastian Huber, embedded brains GmbH Address : Dornierstr. 4, D-82178 Pu

Re: [PATCH 02/17] bsp/arm: Separate setup for translation table

On 02/26/2014 08:03 PM, Gedare Bloom wrote: Perhaps the function should be split in two: arm_cp15_setup_translation_table() I for one, do find this function's name insufficiently descriptive/self-explanatory. What kind of translation does it perform? IRQ-No->IRQ-vector-table-index, utf8->AN

Re: [PATCH 02/17] bsp/arm: Separate setup for translation table

Hi Ralf, Some of these line are far to long. There is no formal policy on this such as 80 columns however some are way way past a reasonable limit. There are also some "/* TODO */" statements. Seems we are supporting doxygen should this be @todo. Also it would be nice if some detail was adde

TCP/IP update, possible SMP (GSOC 2014)

Hey all! I'm a student looking to participate with RTEMS for this year's summer of code. I'm trying to flesh out some good project ideas. I was wondering about the current state of the TCP/IP update, regarding how much and what kind of work is left to be done. The wiki page at TCP/IP_update

Re: [PATCH 6/8] bsp/leon3: Add L2C registers

Maybe it is just me, but l2c looks very close to i2c which might cause some confusion. On Wed, Feb 26, 2014 at 10:52 AM, Sebastian Huber wrote: > --- > c/src/lib/libbsp/sparc/shared/include/grlib.h | 25 > + > 1 files changed, 25 insertions(+), 0 deletions(-) > > diff

Re: [PATCH 1/8] sptests/spcache01: Detect write-through cache

The logic here is that a write-through cache will have written back the lines in vdata, whereas a write-back cache won't since there are no cache conflicts before the invalidation. Did you run this test on a write-through target to verify it works as expected? On Wed, Feb 26, 2014 at 10:52 AM, Seb

Re: [PATCH] altera-cyclone-v: Create new BSP

I skimmed these patches and made notes where I saw anything suspect. I assume you have done the sufficient testing for the altera cyclone v itself, but please also verify you tested for other impacted ARM targets especially the zynq and targets that use the new errata handling (I think one of the l

Re: [PATCH 14/17] bsp/altera-cyclone-v: New BSP

Where is this "hwlib" directory, or how does one get its sources? On Wed, Feb 26, 2014 at 5:52 AM, Ralf Kirchner wrote: > From: Sebastian Huber > > --- > c/src/lib/libbsp/arm/acinclude.m4 |2 + > c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 184 >

Re: [PATCH 14/17] bsp/altera-cyclone-v: New BSP

Sorry, did not see the next patch. ignore my question. On Wed, Feb 26, 2014 at 2:15 PM, Gedare Bloom wrote: > Where is this "hwlib" directory, or how does one get its sources? > > On Wed, Feb 26, 2014 at 5:52 AM, Ralf Kirchner > wrote: >> From: Sebastian Huber >> >> --- >> c/src/lib/libbsp/arm

Re: [PATCH 12/17] libbsp/xilinx-zynq: Share handling for ARM cache controller L2C-310

What tests were used for validation of this implementation and on what zynq target? On Wed, Feb 26, 2014 at 5:51 AM, Ralf Kirchner wrote: > --- > c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am |4 +- > c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h|2 + > c/src/lib/libbsp/arm/xili

Re: [PATCH 01/17] bsp/arm: Invalidate SCU

On Wed, Feb 26, 2014 at 2:01 PM, Gedare Bloom wrote: > On Wed, Feb 26, 2014 at 5:51 AM, Ralf Kirchner > wrote: >> --- >> c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h | 12 >> c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h | 10 ++ >> 2 Dateien geänd

Re: [PATCH 02/17] bsp/arm: Separate setup for translation table

Perhaps the function should be split in two: arm_cp15_setup_translation_table() arm_cp15_enable_mmu_and_cache() ? On Wed, Feb 26, 2014 at 5:51 AM, Ralf Kirchner wrote: > --- > .../lib/libbsp/arm/shared/include/arm-cp15-start.h | 26 > > 1 Datei geändert, 21 Zeilen hinzuge

Re: [PATCH 01/17] bsp/arm: Invalidate SCU

On Wed, Feb 26, 2014 at 5:51 AM, Ralf Kirchner wrote: > --- > c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h | 12 > c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h | 10 ++ > 2 Dateien geändert, 22 Zeilen hinzugefügt(+) > > diff --git a/c/src/lib/libbs

Re: [PATCH 8/8] tmtests/tmcontext01: New test

This looks enormously like the number of register windows in use increasing. What is this like on an ARM? On Feb 26, 2014 5:01 PM, Sebastian Huber wrote: The python script can be used to easily plot the XML output. See attached file with values obtained on the NGMP board. -- Sebastian Huber,

[PATCH 8/8] tmtests/tmcontext01: New test

--- testsuites/tmtests/Makefile.am |1 + testsuites/tmtests/configure.ac|1 + testsuites/tmtests/tmcontext01/Makefile.am | 19 ++ testsuites/tmtests/tmcontext01/init.c | 273 testsuites/tmtests/tmcontext01/plot.py

[PATCH 5/8] bsp/leon3: Add new cache manager implementation

The previous implementation used an instruction cache line size of 0, this is a bogus value. Use a instruction cache line size of 64 since the L2 cache may have a line size of 32 or 64. A greater value should cause no harm. Use a FLUSH operation for _CPU_cache_invalidate_instruction_range(). Th

[PATCH 7/8] bsp/leon3: Add L2 cache support

--- c/src/lib/libbsp/sparc/leon3/include/cache_.h | 81 + 1 files changed, 81 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/sparc/leon3/include/cache_.h b/c/src/lib/libbsp/sparc/leon3/include/cache_.h index eafbb48..32fae4d 100644 --- a/c/src/lib/libbsp/sp

[PATCH 4/8] rtems: Add cache size functions

Add rtems_cache_get_data_cache_size() and rtems_cache_get_instruction_cache_size(). --- c/src/lib/libcpu/shared/src/cache_manager.c | 21 +++ cpukit/rtems/include/rtems/rtems/cache.h| 20 ++ testsuites/sptests/spcache01/init.c | 38

[PATCH 6/8] bsp/leon3: Add L2C registers

--- c/src/lib/libbsp/sparc/shared/include/grlib.h | 25 + 1 files changed, 25 insertions(+), 0 deletions(-) diff --git a/c/src/lib/libbsp/sparc/shared/include/grlib.h b/c/src/lib/libbsp/sparc/shared/include/grlib.h index 9c45038..5a1449f 100644 --- a/c/src/lib/libbsp/sp

[PATCH 2/8] rtems: Cache manager documentation

Move useful functions to the top of the file. --- cpukit/rtems/include/rtems/rtems/cache.h | 145 -- 1 files changed, 79 insertions(+), 66 deletions(-) diff --git a/cpukit/rtems/include/rtems/rtems/cache.h b/cpukit/rtems/include/rtems/rtems/cache.h index 372f8f3..a85

[PATCH 1/8] sptests/spcache01: Detect write-through cache

--- testsuites/sptests/spcache01/init.c| 17 ++--- testsuites/sptests/spcache01/spcache01.scn |1 + 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/testsuites/sptests/spcache01/init.c b/testsuites/sptests/spcache01/init.c index 9f27a79..d9eb053 100644 ---

[PATCH 3/8] rtems: Use size_t for cache line size

A cache line cannot have a negative size. --- c/src/lib/libcpu/bfin/network/ethernet.c |2 +- .../new-exceptions/bspsupport/ppc_exc_alignment.c |2 +- c/src/lib/libcpu/shared/src/cache_manager.c|4 ++-- cpukit/rtems/include/rtems/rtems/cache.h |4 ++--

[PATCH 09/17] bsp/xilinx-zynq: Add arm-errata.h and arm-release-id.h

--- c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am |2 ++ c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am |8 2 Dateien geändert, 10 Zeilen hinzugefügt(+) diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am index f27b66d..8eaf9

[PATCH 03/17] bsp/arm: Add CP15 methods

--- c/src/lib/libcpu/arm/shared/include/arm-cp15.h | 99 +++- 1 Datei geändert, 98 Zeilen hinzugefügt(+), 1 Zeile entfernt(-) diff --git a/c/src/lib/libcpu/arm/shared/include/arm-cp15.h b/c/src/lib/libcpu/arm/shared/include/arm-cp15.h index 43da5a2..dd6bba2 100644 --- a/c/s

[PATCH] altera-cyclone-v: Create new BSP

These patches create a new BSP for the Alteras Cyclone-V. This BSP supports SMP on two cores. It uses a new libchip driver for the Synopsys IP DWMAC 1000 onchip network controller. It suuports the L2C-310 level 2 cache controller from arm in arm/shared/arm-l2c-310/cache_.h. In addition the general

[PATCH 12/17] libbsp/xilinx-zynq: Share handling for ARM cache controller L2C-310

--- c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am |4 +- c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h|2 + c/src/lib/libbsp/arm/xilinx-zynq/include/cache_.h | 986 - 3 Dateien geändert, 4 Zeilen hinzugefügt(+), 988 Zeilen entfernt(-) delete mode 100644 c/src

[PATCH 05/17] bsp/arm: Add arm-errata.h and arm-release-id.h

--- c/src/lib/libbsp/arm/shared/include/arm-errata.h | 127 .../lib/libbsp/arm/shared/include/arm-release-id.h | 152 2 Dateien geändert, 279 Zeilen hinzugefügt(+) create mode 100644 c/src/lib/libbsp/arm/shared/include/arm-errata.h create mode 100644 c/s

[PATCH 07/17] bsp/raspberrypi: Add arm-errata.h and arm-release-id.h

--- c/src/lib/libbsp/arm/raspberrypi/Makefile.am |2 ++ c/src/lib/libbsp/arm/raspberrypi/preinstall.am |8 2 Dateien geändert, 10 Zeilen hinzugefügt(+) diff --git a/c/src/lib/libbsp/arm/raspberrypi/Makefile.am b/c/src/lib/libbsp/arm/raspberrypi/Makefile.am index 3fb0faf..a8d98

[PATCH 01/17] bsp/arm: Invalidate SCU

--- c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h | 12 c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h | 10 ++ 2 Dateien geändert, 22 Zeilen hinzugefügt(+) diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h b/c/src/lib/libbsp/arm/s

[PATCH 08/17] bsp/realview-pbx-a9: Add arm-errata.h and arm-release-id.h

--- c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am |2 ++ c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am |8 2 Dateien geändert, 10 Zeilen hinzugefügt(+) diff --git a/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am b/c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am inde

[PATCH 06/17] bsp/lpc32xx: Add arm-errata.h and arm-release-id.h

--- c/src/lib/libbsp/arm/lpc32xx/Makefile.am |2 ++ c/src/lib/libbsp/arm/lpc32xx/preinstall.am |8 2 Dateien geändert, 10 Zeilen hinzugefügt(+) diff --git a/c/src/lib/libbsp/arm/lpc32xx/Makefile.am b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am index c2c19f6..666ccbe 100644 --- a/

[PATCH 14/17] bsp/altera-cyclone-v: New BSP

From: Sebastian Huber --- c/src/lib/libbsp/arm/acinclude.m4 |2 + c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 184 c/src/lib/libbsp/arm/altera-cyclone-v/bsp_specs| 13 ++ c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac | 47 .../arm

[PATCH 04/17] bsp/arm: Add linker symbol bsp_processor_count

--- c/src/lib/libbsp/arm/shared/include/linker-symbols.h |2 ++ 1 Datei geändert, 2 Zeilen hinzugefügt(+) diff --git a/c/src/lib/libbsp/arm/shared/include/linker-symbols.h b/c/src/lib/libbsp/arm/shared/include/linker-symbols.h index 6555e04..a8d31ac 100644 --- a/c/src/lib/libbsp/arm/shared/i

[PATCH 10/17] bsp/arm: Add SCU errata handling for L2C-310 cache

--- .../libbsp/arm/shared/include/arm-a9mpcore-regs.h |5 ++- .../libbsp/arm/shared/include/arm-a9mpcore-start.h | 35 2 Dateien geändert, 33 Zeilen hinzugefügt(+), 7 Zeilen entfernt(-) diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h b/c/src/lib/l

[PATCH 16/17] bsp/altera-cyclone-v: Made hwlib compile clean

Made Alteras hwlib compile clean within the RTEMS build system --- c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am |1 + .../altera-cyclone-v/hwlib/include/socal/socal.h |4 +- .../hwlib/src/hwmgr/alt_clock_manager.c| 282 +--- 3 Dateien geändert, 6 Zeilen

[PATCH 02/17] bsp/arm: Separate setup for translation table

--- .../lib/libbsp/arm/shared/include/arm-cp15-start.h | 26 1 Datei geändert, 21 Zeilen hinzugefügt(+), 5 Zeilen entfernt(-) diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cp15-start.h b/c/src/lib/libbsp/arm/shared/include/arm-cp15-start.h index 54f2963..a0fe9b1 100

[PATCH] altera-cyclone-v: Create new BSP

These patches create a new BSP for the Alteras Cyclone-V. This BSP supports SMP on two cores. It uses a new libchip driver for the Synopsys IP DWMAC 1000 onchip network controller. It suuports the L2C-310 level 2 cache controller from arm in arm/shared/arm-l2c-310/cache_.h. In addition the general

Re: [PATCH 2/4] score: SMP initialization and shutdown changes

First some words to this patch set. It is a gradual improvement of the existing SMP low-level initialization and shutdown procedure. The existing solution was able to start an SMP system. Only atomic reads/writes were used. It is impossible to implement a controlled shutdown only with atomi

Re: [PATCH 2/4] score: SMP initialization and shutdown changes

On 2014-02-25 00:13, Chris Johns wrote: On 25/02/2014 10:02 am, Chris Johns wrote: Does a LEON3 define START_LEON3_ENABLE_SMP ? I mean LEON4, that is "Does a LEON4 define START_LEON3_ENABLE_SMP ?". There is no specific LEON4 BSP, so LEON3 and LEON4 are currently equal in RTEMS. -- Sebastian

Re: Uniprocessor Tests in SMP Configuration

On 2014-02-24 23:06, Chris Johns wrote: We (= embedded brains) have currently only a budget for 1. That is fine. This is an RTEMS Project issue to resolve and finally accept the patches and I certainly do not expect you to have to find all the funding and complete the work. The RTEMS Project ne