Module Name:src
Committed By: tnn
Date: Sat Nov 11 17:35:45 UTC 2023
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
gicv3_its: assorted minor improvements
- KASSERT that the command queue is not stalled due to async error
before issuing more
Module Name:src
Committed By: tnn
Date: Sat Nov 11 17:35:45 UTC 2023
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
gicv3_its: assorted minor improvements
- KASSERT that the command queue is not stalled due to async error
before issuing more
Module Name:src
Committed By: riastradh
Date: Thu Oct 5 12:30:59 UTC 2023
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
arm/gic: Check l_blcnt, not l_biglocks.
l_biglocks is a now-defunct temporary storage used only when
sleeping; l_blcnt is the number of
Module Name:src
Committed By: riastradh
Date: Thu Oct 5 12:30:59 UTC 2023
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
arm/gic: Check l_blcnt, not l_biglocks.
l_biglocks is a now-defunct temporary storage used only when
sleeping; l_blcnt is the number of
Module Name:src
Committed By: skrll
Date: Sat Nov 19 12:12:26 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: gtmr_var.h
Log Message:
G/C gtmr_init function declaration
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gtmr_var.h
Module Name:src
Committed By: skrll
Date: Sat Nov 19 12:12:26 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: gtmr_var.h
Log Message:
G/C gtmr_init function declaration
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/sys/arch/arm/cortex/gtmr_var.h
Module Name:src
Committed By: jmcneill
Date: Sat Nov 5 17:30:20 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: a9ptmr.c a9ptmr_var.h
Log Message:
Handle speed change events
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/a9ptmr.c
Module Name:src
Committed By: jmcneill
Date: Sat Nov 5 17:30:20 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: a9ptmr.c a9ptmr_var.h
Log Message:
Handle speed change events
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/cortex/a9ptmr.c
Module Name:src
Committed By: jmcneill
Date: Sat Jun 25 18:05:09 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
gicv3: Treat all IPLs below IPL_VM as IPL_NONE for hwpl mappings
To generate a diff of this commit:
cvs rdiff -u -r1.52 -r1.53
Module Name:src
Committed By: jmcneill
Date: Sat Jun 25 18:05:09 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
gicv3: Treat all IPLs below IPL_VM as IPL_NONE for hwpl mappings
To generate a diff of this commit:
cvs rdiff -u -r1.52 -r1.53
Module Name:src
Committed By: riastradh
Date: Mon Mar 28 19:59:36 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
arm/cortex: Use container_of, not bespoke offsetof arithmetic.
To generate a diff of this commit:
cvs rdiff -u -r1.49 -r1.50
Module Name:src
Committed By: riastradh
Date: Mon Mar 28 19:59:36 UTC 2022
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
arm/cortex: Use container_of, not bespoke offsetof arithmetic.
To generate a diff of this commit:
cvs rdiff -u -r1.49 -r1.50
Module Name:src
Committed By: jakllsch
Date: Sat Nov 13 18:30:28 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
fix aarch64 build
To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs
Module Name:src
Committed By: jakllsch
Date: Sat Nov 13 18:30:28 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
fix aarch64 build
To generate a diff of this commit:
cvs rdiff -u -r1.47 -r1.48 src/sys/arch/arm/cortex/gtmr.c
Please note that diffs
Module Name:src
Committed By: skrll
Date: Sun Oct 31 17:24:11 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Fix non-DIAGNOSTIC builds (hopefully). No idea why this didn't fail to
build for me without DIAGNOSTIC.
To generate a diff of this
Module Name:src
Committed By: skrll
Date: Sun Oct 31 17:24:11 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Fix non-DIAGNOSTIC builds (hopefully). No idea why this didn't fail to
build for me without DIAGNOSTIC.
To generate a diff of this
Module Name:src
Committed By: jmcneill
Date: Sun Oct 31 15:32:14 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic_splfuncs_armv8.S
Log Message:
Reload tpidr_el1 into x3 and re-test newipl vs cpl on restart.
To generate a diff of this commit:
cvs rdiff -u -r1.2
Module Name:src
Committed By: jmcneill
Date: Sun Oct 31 15:32:14 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic_splfuncs_armv8.S
Log Message:
Reload tpidr_el1 into x3 and re-test newipl vs cpl on restart.
To generate a diff of this commit:
cvs rdiff -u -r1.2
Module Name:src
Committed By: skrll
Date: Thu Oct 21 04:47:57 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Fix some conditionals to match gicv3 and add some comments to describe
what's going on.
Fixes PR port-evbarm/56420
To generate a diff of
Module Name:src
Committed By: skrll
Date: Thu Oct 21 04:47:57 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic.c
Log Message:
Fix some conditionals to match gicv3 and add some comments to describe
what's going on.
Fixes PR port-evbarm/56420
To generate a diff of
Module Name:src
Committed By: skrll
Date: Sat Oct 2 20:52:09 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: a9tmr_reg.h cpu_in_cksum_asm_neon.S gicv3.c
pl310.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: skrll
Date: Sat Oct 2 20:52:09 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: a9tmr_reg.h cpu_in_cksum_asm_neon.S gicv3.c
pl310.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3
Module Name:src
Committed By: jmcneill
Date: Sun Sep 26 20:55:15 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic_splfuncs.c
Log Message:
Add missing insn barrier
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/gic_splfuncs.c
Module Name:src
Committed By: jmcneill
Date: Sun Sep 26 20:55:15 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gic_splfuncs.c
Log Message:
Add missing insn barrier
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/cortex/gic_splfuncs.c
Module Name:src
Committed By: jmcneill
Date: Sat Sep 11 01:49:12 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
GIC: Support SPI affinity routing before secondary CPUs have hatched.
Instead of reading MPIDR from CPU init to determine a routing
Module Name:src
Committed By: jmcneill
Date: Sat Sep 11 01:49:12 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
GIC: Support SPI affinity routing before secondary CPUs have hatched.
Instead of reading MPIDR from CPU init to determine a routing
Module Name:src
Committed By: jmcneill
Date: Thu Sep 9 21:39:03 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
If we get a spurious interrupt, log a debug message and ignore it.
Otherwise we risk tripping an assertion later on due to an interrupt
Module Name:src
Committed By: jmcneill
Date: Thu Sep 9 21:39:03 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
If we get a spurious interrupt, log a debug message and ignore it.
Otherwise we risk tripping an assertion later on due to an interrupt
Module Name:src
Committed By: jmcneill
Date: Mon Aug 30 22:53:37 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
- Add an isb before cnt[pv]_ctl read
- cntk_ctl is 64-bits
- Do not toggle CNTCTL_IMASK in intr handler, as this may be needed
Module Name:src
Committed By: jmcneill
Date: Mon Aug 30 22:53:37 UTC 2021
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
- Add an isb before cnt[pv]_ctl read
- cntk_ctl is 64-bits
- Do not toggle CNTCTL_IMASK in intr handler, as this may be needed
Module Name:src
Committed By: jmcneill
Date: Thu Sep 5 13:33:11 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
- Use pic_do_pending_ints in intr handler
- Sprinkle isb
- Fix PMR bits detection on eMAG, from OpenBSD
To generate a diff of this
Module Name:src
Committed By: jmcneill
Date: Thu Sep 5 13:33:11 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
- Use pic_do_pending_ints in intr handler
- Sprinkle isb
- Fix PMR bits detection on eMAG, from OpenBSD
To generate a diff of this
Module Name:src
Committed By: skrll
Date: Wed Aug 14 09:20:00 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9ptmr.c
Log Message:
Various fixes / changes
- don't use prescaler
- improve AB_DEBUG output
- fix a9ptmr_delay to work with a decrementing counter!
Thanks
Module Name:src
Committed By: skrll
Date: Wed Aug 14 09:20:00 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9ptmr.c
Log Message:
Various fixes / changes
- don't use prescaler
- improve AB_DEBUG output
- fix a9ptmr_delay to work with a decrementing counter!
Thanks
Module Name:src
Committed By: skrll
Date: Tue Jul 30 06:57:02 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9wdt.c
Log Message:
Fix loop to calculate prescaler divisor.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/a9wdt.c
Module Name:src
Committed By: skrll
Date: Tue Jul 30 06:57:02 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9wdt.c
Log Message:
Fix loop to calculate prescaler divisor.
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/cortex/a9wdt.c
Module Name:src
Committed By: skrll
Date: Sat Jul 27 07:02:09 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9tmr_reg.h
Log Message:
Rename a register define to make it more obvious it's watchdog only
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: skrll
Date: Sat Jul 27 07:02:09 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9tmr_reg.h
Log Message:
Rename a register define to make it more obvious it's watchdog only
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2
Module Name:src
Committed By: jmcneill
Date: Sun Jun 30 17:33:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Cleanup ThunderX quirk and print cache / shareability details for ITT tables
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: jmcneill
Date: Sun Jun 30 17:33:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Cleanup ThunderX quirk and print cache / shareability details for ITT tables
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: jmcneill
Date: Sun Jun 30 11:11:38 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
Fix size of LPI pending table allocation and enable caching of LPI conf
and pending tables where possible.
To generate a diff
Module Name:src
Committed By: jmcneill
Date: Sun Jun 30 11:11:38 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
Fix size of LPI pending table allocation and enable caching of LPI conf
and pending tables where possible.
To generate a diff
Module Name:src
Committed By: jmcneill
Date: Sun Jun 30 10:10:20 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Enable caching of ITS tables when possible
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20
Module Name:src
Committed By: jmcneill
Date: Sun Jun 30 10:10:20 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Enable caching of ITS tables when possible
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20
Module Name:src
Committed By: jmcneill
Date: Sat Jun 29 16:48:07 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Restore original size calculation for MAPD and don't disable MSI/MSIX on
devices before making changes
To generate a diff of this
Module Name:src
Committed By: jmcneill
Date: Sat Jun 29 16:48:07 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Restore original size calculation for MAPD and don't disable MSI/MSIX on
devices before making changes
To generate a diff of this
Module Name:src
Committed By: jmcneill
Date: Sat Jun 29 13:30:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Rename lpi pic to gicv3-its when an ITS is found
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18
Module Name:src
Committed By: jmcneill
Date: Sat Jun 29 13:30:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Rename lpi pic to gicv3-its when an ITS is found
To generate a diff of this commit:
cvs rdiff -u -r1.17 -r1.18
Module Name:src
Committed By: jmcneill
Date: Wed Jun 26 23:10:42 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.h
Log Message:
Remove unused field
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3.h
Please note that
Module Name:src
Committed By: jmcneill
Date: Wed Jun 26 23:10:42 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.h
Log Message:
Remove unused field
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/cortex/gicv3.h
Please note that
Module Name:src
Committed By: jmcneill
Date: Wed Jun 26 23:00:10 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Change how we detect secure vs non-secure access.
Write 0xff to ICC_PMR_EL1 and read back how many bits are implemented,
then do the
Module Name:src
Committed By: jmcneill
Date: Wed Jun 26 23:00:10 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Change how we detect secure vs non-secure access.
Write 0xff to ICC_PMR_EL1 and read back how many bits are implemented,
then do the
Module Name:src
Committed By: jmcneill
Date: Sun Jun 23 16:19:51 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Pass correct EventID to MOVI and INV commands
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17
Module Name:src
Committed By: jmcneill
Date: Sun Jun 23 16:19:51 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Pass correct EventID to MOVI and INV commands
To generate a diff of this commit:
cvs rdiff -u -r1.16 -r1.17
Module Name:src
Committed By: jmcneill
Date: Sun Jun 23 16:04:52 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Remove unused variable (build fix)
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16
Module Name:src
Committed By: jmcneill
Date: Sun Jun 23 16:03:30 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Ensure that the "size" parameter of MAPD matches the size of the ITT being
mapped and subtract the LPI base from EventID. Fixes
Module Name:src
Committed By: jmcneill
Date: Sun Jun 23 16:03:30 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Ensure that the "size" parameter of MAPD matches the size of the ITT being
mapped and subtract the LPI base from EventID. Fixes
Module Name:src
Committed By: jmcneill
Date: Mon Jun 17 10:15:08 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
Improve priority handling for cases where access is secure, from OpenBSD.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: jmcneill
Date: Mon Jun 17 10:15:08 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c gicv3.h
Log Message:
Improve priority handling for cases where access is secure, from OpenBSD.
To generate a diff of this commit:
cvs rdiff -u
Module Name:src
Committed By: jmcneill
Date: Mon Jun 17 00:49:55 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
- Disable MSI/MSI-X when making changes
- MSI: Write the vector count to the Multi Message Enable (MME) field
- MSI: Set DATA to the
Module Name:src
Committed By: jmcneill
Date: Mon Jun 17 00:49:55 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gic_v2m.c
Log Message:
- Disable MSI/MSI-X when making changes
- MSI: Write the vector count to the Multi Message Enable (MME) field
- MSI: Set DATA to the
Module Name:src
Committed By: jmcneill
Date: Sun Jun 16 19:19:30 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Pass correct event ID with MOVI commands
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14
Module Name:src
Committed By: jmcneill
Date: Sun Jun 16 19:19:30 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
Pass correct event ID with MOVI commands
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14
Module Name:src
Committed By: jmcneill
Date: Sun Jun 16 11:05:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
- Disable MSI/MSI-X when making changes
- MSI: Write the vector count to the Multi Message Enable (MME) field
- MSI: Set DATA to the
Module Name:src
Committed By: jmcneill
Date: Sun Jun 16 11:05:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c
Log Message:
- Disable MSI/MSI-X when making changes
- MSI: Write the vector count to the Multi Message Enable (MME) field
- MSI: Set DATA to the
Module Name:src
Committed By: jmcneill
Date: Sun Jun 16 10:57:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gtmr.c
Log Message:
Disable counter before updating cval/tval
To generate a diff of this commit:
cvs rdiff -u -r1.39 -r1.40 src/sys/arch/arm/cortex/gtmr.c
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 21:02:07 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h
Log Message:
Allow set_affinity calls before PEs are brought online. We store the
desired target PE if set_affinity is called early
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 21:02:07 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h
Log Message:
Allow set_affinity calls before PEs are brought online. We store the
desired target PE if set_affinity is called early
Module Name:src
Committed By: mrg
Date: Wed Jun 12 11:35:18 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
revert rev 1.4:
>Adjust priority mappings, NFCI
it has some unintended change that makes nvme hangy. ok @jmcneill.
To generate a diff of
Module Name:src
Committed By: mrg
Date: Wed Jun 12 11:35:18 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
revert rev 1.4:
>Adjust priority mappings, NFCI
it has some unintended change that makes nvme hangy. ok @jmcneill.
To generate a diff of
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:27:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Revert "Route all interrupts to the primary PE by default"
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:27:59 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Revert "Route all interrupts to the primary PE by default"
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:03:28 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Route all interrupts to the primary PE by default
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:03:28 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Route all interrupts to the primary PE by default
To generate a diff of this commit:
cvs rdiff -u -r1.14 -r1.15
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:02:17 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Adjust priority mappings, NFCI
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3.c
Please
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:02:17 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3.c
Log Message:
Adjust priority mappings, NFCI
To generate a diff of this commit:
cvs rdiff -u -r1.13 -r1.14 src/sys/arch/arm/cortex/gicv3.c
Please
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:00:09 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h
Log Message:
Fail gracefully if gicv3_its_set_affinity is called before a cpu is
brought online.
To generate a diff of this commit:
Module Name:src
Committed By: jmcneill
Date: Wed Jun 12 10:00:09 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: gicv3_its.c gicv3_its.h
Log Message:
Fail gracefully if gicv3_its_set_affinity is called before a cpu is
brought online.
To generate a diff of this commit:
Module Name:src
Committed By: skrll
Date: Tue Jun 11 12:48:30 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9tmr.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/a9tmr.c
Please note that diffs
Module Name:src
Committed By: skrll
Date: Tue Jun 11 12:48:30 UTC 2019
Modified Files:
src/sys/arch/arm/cortex: a9tmr.c
Log Message:
Trailing whitespace
To generate a diff of this commit:
cvs rdiff -u -r1.19 -r1.20 src/sys/arch/arm/cortex/a9tmr.c
Please note that diffs
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