CVS commit: src/sys/arch/x86/include

2022-01-29 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Sat Jan 29 08:18:22 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Intel Hybrid Information Enumeration (CPUID Fn_001a). To generate a diff of this commit: cvs rdiff -u -r1.187 -r1.188 src/

CVS commit: src/sys/arch/x86/include

2022-01-15 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Sat Jan 15 10:59:40 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Some definitions from AMD APM: - CPUID Fn8001 %ecx bit 30 AddrMaskExt. - CPUID Fn8008 %ebx bit 13 INT_WBINVD. - CPUI

CVS commit: src/sys/arch/x86/include

2022-01-15 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Sat Jan 15 10:59:40 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Some definitions from AMD APM: - CPUID Fn8001 %ecx bit 30 AddrMaskExt. - CPUID Fn8008 %ebx bit 13 INT_WBINVD. - CPUI

CVS commit: src/sys/arch/x86/include

2022-01-15 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Sat Jan 15 10:09:15 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Whitespace. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.184 -r1.185 src/sys/arch/x86/include/special

CVS commit: src/sys/arch/x86/include

2022-01-15 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Sat Jan 15 10:09:15 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Whitespace. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.184 -r1.185 src/sys/arch/x86/include/special

CVS commit: src/sys/arch/x86/include

2022-01-15 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Sat Jan 15 09:58:23 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Move CPUID_CAPEX_FLAGS next to %eax because it's for %eax. To generate a diff of this commit: cvs rdiff -u -r1.183 -r1.184 src/sys

CVS commit: src/sys/arch/x86/include

2022-01-15 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Sat Jan 15 09:58:23 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Move CPUID_CAPEX_FLAGS next to %eax because it's for %eax. To generate a diff of this commit: cvs rdiff -u -r1.183 -r1.184 src/sys

CVS commit: src/sys/arch/x86/include

2022-01-15 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Sat Jan 15 09:55:14 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: No functional change. - Modify comment. Add comment. Fix typo. Mainly taken from dragonfly. - Use __BIT(). To generate a diff o

CVS commit: src/sys/arch/x86/include

2022-01-15 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Sat Jan 15 09:55:14 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: No functional change. - Modify comment. Add comment. Fix typo. Mainly taken from dragonfly. - Use __BIT(). To generate a diff o

CVS commit: src/sys/arch/x86/x86

2022-01-14 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Fri Jan 14 15:48:51 UTC 2022 Modified Files: src/sys/arch/x86/x86: procfs_machdep.c Log Message: Update for cpuid flags: - The table 11 was changed from CPUID 0x0f leaf 0 %edx to a Linux mapping. - The table 12 was changed fro

CVS commit: src/sys/arch/x86/x86

2022-01-14 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Fri Jan 14 15:48:51 UTC 2022 Modified Files: src/sys/arch/x86/x86: procfs_machdep.c Log Message: Update for cpuid flags: - The table 11 was changed from CPUID 0x0f leaf 0 %edx to a Linux mapping. - The table 12 was changed fro

CVS commit: src/sys/arch/x86/include

2022-01-14 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Fri Jan 14 15:46:41 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Architectural LBR and Linear Address Masking. To generate a diff of this commit: cvs rdiff -u -r1.181 -r1.182 src/sys/arch/x86

CVS commit: src/sys/arch/x86/include

2022-01-14 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Fri Jan 14 15:46:41 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add Architectural LBR and Linear Address Masking. To generate a diff of this commit: cvs rdiff -u -r1.181 -r1.182 src/sys/arch/x86

CVS commit: src/sys/arch/x86/include

2022-01-14 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Fri Jan 14 15:45:53 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Both Intel and AMD says the name of CPUID 0x01 %edx bit 19 is "CLFSH". To generate a diff of this commit: cvs rdiff -u -r1.180 -r1

CVS commit: src/sys/arch/x86/include

2022-01-14 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Fri Jan 14 15:45:53 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Both Intel and AMD says the name of CPUID 0x01 %edx bit 19 is "CLFSH". To generate a diff of this commit: cvs rdiff -u -r1.180 -r1

CVS commit: src/sys/arch/x86/include

2022-01-13 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Thu Jan 13 16:03:38 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add some CPUID bits from the latest Intel SDM. - Last Branch Record. - Thread Director. - AVX version of VNNI. - Fast short REP

CVS commit: src/sys/arch/x86/include

2022-01-13 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Thu Jan 13 16:03:38 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add some CPUID bits from the latest Intel SDM. - Last Branch Record. - Thread Director. - AVX version of VNNI. - Fast short REP

CVS commit: src/sys/arch/x86/include

2022-01-12 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Thu Jan 13 00:21:41 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Use __BIT(). KNF. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.178 -r1.179 src/sys/arch/x86/include/

CVS commit: src/sys/arch/x86/include

2022-01-12 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Thu Jan 13 00:21:41 UTC 2022 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Use __BIT(). KNF. No functional change. To generate a diff of this commit: cvs rdiff -u -r1.178 -r1.179 src/sys/arch/x86/include/

CVS commit: src/sys/arch/x86/x86

2021-12-22 Thread Shoichi YAMAGUCHI
Module Name:src Committed By: yamaguchi Date: Thu Dec 23 02:45:44 UTC 2021 Modified Files: src/sys/arch/x86/x86: intr.c Log Message: Move the variable into the section that uses it To generate a diff of this commit: cvs rdiff -u -r1.158 -r1.159 src/sys/arch/x86/x86/intr.

CVS commit: src/sys/arch/x86/x86

2021-12-22 Thread Shoichi YAMAGUCHI
Module Name:src Committed By: yamaguchi Date: Thu Dec 23 02:45:44 UTC 2021 Modified Files: src/sys/arch/x86/x86: intr.c Log Message: Move the variable into the section that uses it To generate a diff of this commit: cvs rdiff -u -r1.158 -r1.159 src/sys/arch/x86/x86/intr.

CVS commit: src/sys/arch/x86/x86

2021-12-22 Thread Shoichi YAMAGUCHI
Module Name:src Committed By: yamaguchi Date: Thu Dec 23 02:10:53 UTC 2021 Modified Files: src/sys/arch/x86/x86: intr.c Log Message: delete the extra space To generate a diff of this commit: cvs rdiff -u -r1.157 -r1.158 src/sys/arch/x86/x86/intr.c Please note that diffs

CVS commit: src/sys/arch/x86/x86

2021-12-22 Thread Shoichi YAMAGUCHI
Module Name:src Committed By: yamaguchi Date: Thu Dec 23 02:10:53 UTC 2021 Modified Files: src/sys/arch/x86/x86: intr.c Log Message: delete the extra space To generate a diff of this commit: cvs rdiff -u -r1.157 -r1.158 src/sys/arch/x86/x86/intr.c Please note that diffs

CVS commit: src/sys/arch/x86/include

2021-12-09 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Thu Dec 9 14:33:19 UTC 2021 Modified Files: src/sys/arch/x86/include: cacheinfo.h Log Message: Print TLB message consistently to improve readability. Example: cpu0: L2 cache: 256KB 64B/line 4-way cpu0: L3 cache: 4MB 64B/line

CVS commit: src/sys/arch/x86/include

2021-12-09 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Thu Dec 9 14:33:19 UTC 2021 Modified Files: src/sys/arch/x86/include: cacheinfo.h Log Message: Print TLB message consistently to improve readability. Example: cpu0: L2 cache: 256KB 64B/line 4-way cpu0: L3 cache: 4MB 64B/line

CVS commit: src/sys/arch/x86/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 19:04:04 UTC 2021 Modified Files: src/sys/arch/x86/pci: dwiic_pci.c Log Message: Add more Jasper Lake and Elkhart Lake devices. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/x86/pci/dwiic_p

CVS commit: src/sys/arch/x86/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 19:04:04 UTC 2021 Modified Files: src/sys/arch/x86/pci: dwiic_pci.c Log Message: Add more Jasper Lake and Elkhart Lake devices. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/sys/arch/x86/pci/dwiic_p

CVS commit: src/sys/arch/x86/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 14:53:12 UTC 2021 Modified Files: src/sys/arch/x86/pci: dwiic_pci.c Log Message: Add many Intel I2C devices. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/x86/pci/dwiic_pci.c Please note t

CVS commit: src/sys/arch/x86/pci

2021-10-27 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 27 14:53:12 UTC 2021 Modified Files: src/sys/arch/x86/pci: dwiic_pci.c Log Message: Add many Intel I2C devices. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/x86/pci/dwiic_pci.c Please note t

CVS commit: src/sys/arch/x86/isa

2021-10-16 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sat Oct 16 13:15:01 UTC 2021 Modified Files: src/sys/arch/x86/isa: isa_machdep.c Log Message: Skip legacy device detection for VMware guests with ACPI enabled. To generate a diff of this commit: cvs rdiff -u -r1.48 -r1.49 src/

CVS commit: src/sys/arch/x86/isa

2021-10-16 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Sat Oct 16 13:15:01 UTC 2021 Modified Files: src/sys/arch/x86/isa: isa_machdep.c Log Message: Skip legacy device detection for VMware guests with ACPI enabled. To generate a diff of this commit: cvs rdiff -u -r1.48 -r1.49 src/

Re: CVS commit: src/sys/arch/x86/x86

2021-10-15 Thread Paul Goyette
hehehe - porn iterators - love it! On Fri, 15 Oct 2021, Jason Thorpe wrote: I demand this change be reverted. (/s) On Oct 15, 2021, at 11:12 AM, Jared D. McNeill wrote: Module Name:src Committed By: jmcneill Date: Fri Oct 15 18:12:48 UTC 2021 Modified Files: src/s

CVS commit: src/sys/arch/x86/isa

2021-10-15 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Fri Oct 15 19:01:52 UTC 2021 Modified Files: src/sys/arch/x86/isa: isa_machdep.c Log Message: Add missing acpi include To generate a diff of this commit: cvs rdiff -u -r1.47 -r1.48 src/sys/arch/x86/isa/isa_machdep.c Please no

CVS commit: src/sys/arch/x86/isa

2021-10-15 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Fri Oct 15 19:01:52 UTC 2021 Modified Files: src/sys/arch/x86/isa: isa_machdep.c Log Message: Add missing acpi include To generate a diff of this commit: cvs rdiff -u -r1.47 -r1.48 src/sys/arch/x86/isa/isa_machdep.c Please no

Re: CVS commit: src/sys/arch/x86/x86

2021-10-15 Thread Jason Thorpe
I demand this change be reverted. (/s) > On Oct 15, 2021, at 11:12 AM, Jared D. McNeill wrote: > > Module Name: src > Committed By: jmcneill > Date: Fri Oct 15 18:12:48 UTC 2021 > > Modified Files: > src/sys/arch/x86/x86: tsc.c > > Log Message: > Fix typo in comment: "porniters

CVS commit: src/sys/arch/x86/pci

2021-10-15 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Fri Oct 15 18:51:39 UTC 2021 Modified Files: src/sys/arch/x86/pci: pci_machdep.c Log Message: Disable MSI and MSI-X support if IAPC_BOOT_ARCH reports that MSI is not supported. To generate a diff of this commit: cvs rdiff -u -

CVS commit: src/sys/arch/x86/pci

2021-10-15 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Fri Oct 15 18:51:39 UTC 2021 Modified Files: src/sys/arch/x86/pci: pci_machdep.c Log Message: Disable MSI and MSI-X support if IAPC_BOOT_ARCH reports that MSI is not supported. To generate a diff of this commit: cvs rdiff -u -

CVS commit: src/sys/arch/x86/isa

2021-10-15 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Fri Oct 15 18:44:53 UTC 2021 Modified Files: src/sys/arch/x86/isa: isa_machdep.c Log Message: If ACPI indicates that there are no user visible devices on the LPC or ISA bus, set the "no-legacy-devices" property on isa to bypass

CVS commit: src/sys/arch/x86/isa

2021-10-15 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Fri Oct 15 18:44:53 UTC 2021 Modified Files: src/sys/arch/x86/isa: isa_machdep.c Log Message: If ACPI indicates that there are no user visible devices on the LPC or ISA bus, set the "no-legacy-devices" property on isa to bypass

CVS commit: src/sys/arch/x86/x86

2021-10-15 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Fri Oct 15 18:12:48 UTC 2021 Modified Files: src/sys/arch/x86/x86: tsc.c Log Message: Fix typo in comment: "porniters" -> "pointers" To generate a diff of this commit: cvs rdiff -u -r1.56 -r1.57 src/sys/arch/x86/x86/tsc.c Ple

CVS commit: src/sys/arch/x86/x86

2021-10-15 Thread Jared D. McNeill
Module Name:src Committed By: jmcneill Date: Fri Oct 15 18:12:48 UTC 2021 Modified Files: src/sys/arch/x86/x86: tsc.c Log Message: Fix typo in comment: "porniters" -> "pointers" To generate a diff of this commit: cvs rdiff -u -r1.56 -r1.57 src/sys/arch/x86/x86/tsc.c Ple

CVS commit: src/sys/arch/x86/x86

2021-10-07 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Thu Oct 7 12:52:27 UTC 2021 Modified Files: src/sys/arch/x86/x86: bus_dma.c bus_space.c consinit.c coretemp.c cpu.c cpu_rng.c db_memrw.c efi.c errata.c est.c identcpu.c intel_busclock.c intr.c ioapic.c lap

CVS commit: src/sys/arch/x86/x86

2021-10-07 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Thu Oct 7 12:52:27 UTC 2021 Modified Files: src/sys/arch/x86/x86: bus_dma.c bus_space.c consinit.c coretemp.c cpu.c cpu_rng.c db_memrw.c efi.c errata.c est.c identcpu.c intel_busclock.c intr.c ioapic.c lap

CVS commit: src/sys/arch/x86/x86

2021-10-03 Thread Frederic Cambus
Module Name:src Committed By: fcambus Date: Sun Oct 3 18:47:16 UTC 2021 Modified Files: src/sys/arch/x86/x86: multiboot2.c Log Message: Fix typo when erroring out on unknown ELF machine type. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/x86/x

CVS commit: src/sys/arch/x86/x86

2021-10-03 Thread Frederic Cambus
Module Name:src Committed By: fcambus Date: Sun Oct 3 18:47:16 UTC 2021 Modified Files: src/sys/arch/x86/x86: multiboot2.c Log Message: Fix typo when erroring out on unknown ELF machine type. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/x86/x

CVS commit: src/sys/arch/x86/include

2021-09-30 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Thu Sep 30 15:54:55 UTC 2021 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Print CPUID_PBE (Pending Break Enable) with "PBE". To generate a diff of this commit: cvs rdiff -u -r1.177 -r1.178 src/sys/arch/x8

CVS commit: src/sys/arch/x86/include

2021-09-30 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Thu Sep 30 15:54:55 UTC 2021 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Print CPUID_PBE (Pending Break Enable) with "PBE". To generate a diff of this commit: cvs rdiff -u -r1.177 -r1.178 src/sys/arch/x8

Re: CVS commit: src/sys/arch/x86

2020-08-01 Thread Taylor R Campbell
> Module Name:src > Committed By: jdolecek > Date: Sat Aug 1 12:36:36 UTC 2020 > > Modified Files: > src/sys/arch/x86/pci: pci_intr_machdep.c > src/sys/arch/x86/x86: mainbus.c > > Log Message: > reorder includes to pull __HAVE_PCI_MSI_MSIX properly via > If req

re: CVS commit: src/sys/arch/x86/x86

2020-06-24 Thread matthew green
"Jaromir Dolecek" writes: > Module Name: src > Committed By: jdolecek > Date: Wed Jun 24 22:28:08 UTC 2020 > > Modified Files: > src/sys/arch/x86/x86: multiboot2.c > > Log Message: > don't try allocating 16KB of scratch space on stack > > it's too early for kmem_alloc(), so use st

Re: CVS commit: src/sys/arch/x86/x86

2020-06-24 Thread Joerg Sonnenberger
On Wed, Jun 24, 2020 at 10:28:08PM +, Jaromir Dolecek wrote: > Module Name: src > Committed By: jdolecek > Date: Wed Jun 24 22:28:08 UTC 2020 > > Modified Files: > src/sys/arch/x86/x86: multiboot2.c > > Log Message: > don't try allocating 16KB of scratch space on stack > > it'

Re: CVS commit: src/sys/arch/x86/x86

2020-06-06 Thread Christos Zoulas
In article <20200606135850.ge14...@pony.stderr.spb.ru>, Valery Ushakov wrote: >On Sat, Jun 06, 2020 at 11:25:19 +0200, Kamil Rytarowski wrote: > >> On 06.06.2020 09:42, Simon Burge wrote: >> > "Kamil Rytarowski" wrote: >> > >> >> Module Name: src >> >> Committed By: kamil >> >> Date:

Re: CVS commit: src/sys/arch/x86/x86

2020-06-06 Thread Valery Ushakov
On Sat, Jun 06, 2020 at 11:25:19 +0200, Kamil Rytarowski wrote: > On 06.06.2020 09:42, Simon Burge wrote: > > "Kamil Rytarowski" wrote: > > > >> Module Name: src > >> Committed By: kamil > >> Date: Fri Jun 5 21:48:04 UTC 2020 > >> > >> Modified Files: > >> > >>src/sys

Re: CVS commit: src/sys/arch/x86/x86

2020-06-06 Thread Kamil Rytarowski
On 06.06.2020 09:42, Simon Burge wrote: > "Kamil Rytarowski" wrote: > >> Module Name: src >> Committed By:kamil >> Date:Fri Jun 5 21:48:04 UTC 2020 >> >> Modified Files: >> >> src/sys/arch/x86/x86: cpu_rng.c >> >> Log Message: >> >> Change const unsigned to preprocess

Re: CVS commit: src/sys/arch/x86/x86

2020-06-06 Thread Simon Burge
"Kamil Rytarowski" wrote: > Module Name: src > Committed By: kamil > Date: Fri Jun 5 21:48:04 UTC 2020 > > Modified Files: > > src/sys/arch/x86/x86: cpu_rng.c > > Log Message: > > Change const unsigned to preprocessor define > > Fixes GCC -O0 build with the stack protector. Surely

Re: CVS commit: src/sys/arch/x86/x86

2020-04-02 Thread Kengo NAKAHARA
Hi, Hmm, but TSC drift is still observed on recent (high clock) CPUs. I will have researched and fix later. On 2020/04/03 12:05, Kengo NAKAHARA wrote: Module Name:src Committed By: knakahara Date: Fri Apr 3 03:05:39 UTC 2020 Modified Files: src/sys/arch/x86/x86: tsc.c

Re: CVS commit: src/sys/arch/x86/acpi

2020-03-18 Thread Martin Husemann
On Wed, Mar 18, 2020 at 09:44:03PM +0200, Yorick Hardy wrote: > Dear Andrew, > > On 2020-03-14, Andrew Doran wrote: > > Module Name:src > > Committed By: ad > > Date: Sat Mar 14 13:50:46 UTC 2020 > > > > Modified Files: > > src/sys/arch/x86/acpi: acpi_cpu_md.c > >

Re: CVS commit: src/sys/arch/x86/acpi

2020-03-18 Thread Yorick Hardy
Dear Andrew, On 2020-03-14, Andrew Doran wrote: > Module Name: src > Committed By: ad > Date: Sat Mar 14 13:50:46 UTC 2020 > > Modified Files: > src/sys/arch/x86/acpi: acpi_cpu_md.c > > Log Message: > Put ACPI idle under ACPICPU_ENABLE_C3 until the wrinkles are ironed out. > This

Re: CVS commit: src/sys/arch/x86/x86

2020-03-17 Thread Andrew Doran
On Tue, Mar 17, 2020 at 10:38:14PM +, Andrew Doran wrote: > Log Message: > - Change some expensive checks DEBUG -> DIAGNOSTIC. That was meant to be the other way around, oops. Andrew

Re: CVS commit: src/sys/arch/x86

2020-01-12 Thread Jason Thorpe
We should absolutely verify this under DEBUG. -- thorpej Sent from my iPhone. > On Jan 12, 2020, at 11:25 AM, Joerg Sonnenberger wrote: > > On Sun, Jan 12, 2020 at 01:01:12PM +, Andrew Doran wrote: >> Module Name:src >> Committed By:ad >> Date:Sun Jan 12 13:01:12 UTC 2020 >

Re: CVS commit: src/sys/arch/x86

2020-01-12 Thread Andrew Doran
On Sun, Jan 12, 2020 at 08:25:27PM +0100, Joerg Sonnenberger wrote: > On Sun, Jan 12, 2020 at 01:01:12PM +, Andrew Doran wrote: > > Module Name:src > > Committed By: ad > > Date: Sun Jan 12 13:01:12 UTC 2020 > > > > Modified Files: > > src/sys/arch/x86/include:

Re: CVS commit: src/sys/arch/x86

2020-01-12 Thread Joerg Sonnenberger
On Sun, Jan 12, 2020 at 01:01:12PM +, Andrew Doran wrote: > Module Name: src > Committed By: ad > Date: Sun Jan 12 13:01:12 UTC 2020 > > Modified Files: > src/sys/arch/x86/include: pmap.h pmap_pv.h > src/sys/arch/x86/x86: pmap.c vm_machdep.c x86_tlb.c > > Log Message: > x

Re: CVS commit: src/sys/arch/x86/x86

2019-12-03 Thread Andrew Doran
On Tue, Dec 03, 2019 at 01:14:14PM +0100, Kamil Rytarowski wrote: > On 03.12.2019 12:50, Juergen Hannken-Illjes wrote: > > Module Name:src > > Committed By: hannken > > Date: Tue Dec 3 11:50:45 UTC 2019 > > > > Modified Files: > > src/sys/arch/x86/x86: x86_machdep

Re: CVS commit: src/sys/arch/x86/x86

2019-12-03 Thread Kamil Rytarowski
On 03.12.2019 12:50, Juergen Hannken-Illjes wrote: > Module Name: src > Committed By: hannken > Date: Tue Dec 3 11:50:45 UTC 2019 > > Modified Files: > src/sys/arch/x86/x86: x86_machdep.c > > Log Message: > Make sure the assignment to "idepth" is done inside the loop to prevent >

CVS commit: src/sys/arch/x86

2019-11-29 Thread NONAKA Kimihiro
Module Name:src Committed By: nonaka Date: Sat Nov 30 05:28:28 UTC 2019 Modified Files: src/sys/arch/x86/include: genfb_machdep.h src/sys/arch/x86/x86: genfb_machdep.c hyperv.c Log Message: Prevent panic when attaching genfb if using a serial console with Hyper-V G

CVS commit: src/sys/arch/x86

2019-11-29 Thread NONAKA Kimihiro
Module Name:src Committed By: nonaka Date: Sat Nov 30 05:28:28 UTC 2019 Modified Files: src/sys/arch/x86/include: genfb_machdep.h src/sys/arch/x86/x86: genfb_machdep.c hyperv.c Log Message: Prevent panic when attaching genfb if using a serial console with Hyper-V G

Re: CVS commit: src/sys/arch/x86

2019-11-27 Thread Alexander Nasonov
Maxime Villard wrote: > Module Name: src > Committed By: maxv > Date: Wed Nov 27 06:24:33 UTC 2019 > > Modified Files: > src/sys/arch/x86/include: cpu.h fpu.h > src/sys/arch/x86/x86: cpu.c fpu.c > > Log Message: > Add a small API for in-kernel FPU operations. > > fpu_k

CVS commit: src/sys/arch/x86

2019-11-26 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Wed Nov 27 06:24:33 UTC 2019 Modified Files: src/sys/arch/x86/include: cpu.h fpu.h src/sys/arch/x86/x86: cpu.c fpu.c Log Message: Add a small API for in-kernel FPU operations. fpu_kern_enter(); /* do FPU stu

CVS commit: src/sys/arch/x86

2019-11-26 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Wed Nov 27 06:24:33 UTC 2019 Modified Files: src/sys/arch/x86/include: cpu.h fpu.h src/sys/arch/x86/x86: cpu.c fpu.c Log Message: Add a small API for in-kernel FPU operations. fpu_kern_enter(); /* do FPU stu

CVS commit: src/sys/arch/x86

2019-11-21 Thread Andrew Doran
Module Name:src Committed By: ad Date: Thu Nov 21 21:48:34 UTC 2019 Modified Files: src/sys/arch/x86/include: cpu.h src/sys/arch/x86/x86: x86_tlb.c Log Message: x86 TLB shootdown IPI changes: - Shave some time off processing. - Reduce cacheline/bus traffic on syst

CVS commit: src/sys/arch/x86

2019-11-21 Thread Andrew Doran
Module Name:src Committed By: ad Date: Thu Nov 21 21:48:34 UTC 2019 Modified Files: src/sys/arch/x86/include: cpu.h src/sys/arch/x86/x86: x86_tlb.c Log Message: x86 TLB shootdown IPI changes: - Shave some time off processing. - Reduce cacheline/bus traffic on syst

CVS commit: src/sys/arch/x86/include

2019-11-17 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Sun Nov 17 15:31:05 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add the following bit definitions from the latest Intel SDM: - CET shadow stack - Fast Short REP MOV - Hybrid part - CET Indirec

CVS commit: src/sys/arch/x86/include

2019-11-17 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Sun Nov 17 15:31:05 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: Add the following bit definitions from the latest Intel SDM: - CET shadow stack - Fast Short REP MOV - Hybrid part - CET Indirec

CVS commit: src/sys/arch/x86/x86

2019-11-16 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Nov 16 10:19:29 UTC 2019 Modified Files: src/sys/arch/x86/x86: pmap.c Log Message: Add a NULL check on the structure pointer, not to retrieve its first field if it is NULL. The previous code was not buggy strictly speaking. This

CVS commit: src/sys/arch/x86/x86

2019-11-16 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Sat Nov 16 10:19:29 UTC 2019 Modified Files: src/sys/arch/x86/x86: pmap.c Log Message: Add a NULL check on the structure pointer, not to retrieve its first field if it is NULL. The previous code was not buggy strictly speaking. This

CVS commit: src/sys/arch/x86

2019-11-13 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Wed Nov 13 12:55:10 UTC 2019 Modified Files: src/sys/arch/x86/include: pmap.h pmap_pv.h src/sys/arch/x86/x86: pmap.c Log Message: Rename: PP_ATTRS_M -> PP_ATTRS_D PP_ATTRS_U -> PP_ATTRS_A For consistency. T

CVS commit: src/sys/arch/x86

2019-11-13 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Wed Nov 13 12:55:10 UTC 2019 Modified Files: src/sys/arch/x86/include: pmap.h pmap_pv.h src/sys/arch/x86/x86: pmap.c Log Message: Rename: PP_ATTRS_M -> PP_ATTRS_D PP_ATTRS_U -> PP_ATTRS_A For consistency. T

CVS commit: src/sys/arch/x86/pci

2019-11-12 Thread Hikaru Abe
Module Name:src Committed By: hikaru Date: Wed Nov 13 02:55:00 UTC 2019 Modified Files: src/sys/arch/x86/pci: msipic.c Log Message: Disable MSI-X before writing the MSI-X table. That fixes MSI-X interrupt lost on VMware ESXi 6.7 PCI passthrough devices. ok knakahara@ T

CVS commit: src/sys/arch/x86/pci

2019-11-12 Thread Hikaru Abe
Module Name:src Committed By: hikaru Date: Wed Nov 13 02:55:00 UTC 2019 Modified Files: src/sys/arch/x86/pci: msipic.c Log Message: Disable MSI-X before writing the MSI-X table. That fixes MSI-X interrupt lost on VMware ESXi 6.7 PCI passthrough devices. ok knakahara@ T

Re: CVS commit: src/sys/arch/x86

2019-11-12 Thread Christoph Badura
Hi, On Tue, Nov 12, 2019 at 06:00:13PM +, Maxime Villard wrote: > Committed By: maxv > Date: Tue Nov 12 18:00:13 UTC 2019 > Modified Files: > src/sys/arch/x86/include: specialreg.h > src/sys/arch/x86/x86: spectre.c > Log Message: > Mitigation for CVE-2019-11135: TSX Asynchr

CVS commit: src/sys/arch/x86

2019-11-12 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Tue Nov 12 18:00:13 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h src/sys/arch/x86/x86: spectre.c Log Message: Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA). Two sysctls are added: m

CVS commit: src/sys/arch/x86

2019-11-12 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Tue Nov 12 18:00:13 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h src/sys/arch/x86/x86: spectre.c Log Message: Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA). Two sysctls are added: m

CVS commit: src/sys/arch/x86/x86

2019-11-07 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Fri Nov 8 04:15:02 UTC 2019 Modified Files: src/sys/arch/x86/x86: intr.c Log Message: Fix a bug that evcnt_detach() called twice when the idt vector is full. OK'd by knakahara. To generate a diff of this commit: cvs rdiff -u

CVS commit: src/sys/arch/x86/x86

2019-11-07 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Fri Nov 8 04:15:02 UTC 2019 Modified Files: src/sys/arch/x86/x86: intr.c Log Message: Fix a bug that evcnt_detach() called twice when the idt vector is full. OK'd by knakahara. To generate a diff of this commit: cvs rdiff -u

CVS commit: src/sys/arch/x86/acpi

2019-11-05 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Tue Nov 5 20:21:34 UTC 2019 Modified Files: src/sys/arch/x86/acpi: acpi_cpu_md.c Log Message: Add the __nocsan attribute on this function. Races on ci_want_resched are accepted (part of the design). To generate a diff of this com

CVS commit: src/sys/arch/x86/acpi

2019-11-05 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Tue Nov 5 20:21:34 UTC 2019 Modified Files: src/sys/arch/x86/acpi: acpi_cpu_md.c Log Message: Add the __nocsan attribute on this function. Races on ci_want_resched are accepted (part of the design). To generate a diff of this com

CVS commit: src/sys/arch/x86/x86

2019-11-01 Thread Takahiro Kambe
Module Name:src Committed By: taca Date: Fri Nov 1 15:01:27 UTC 2019 Modified Files: src/sys/arch/x86/x86: cpu_rng.c Log Message: Check CPU support of RDRAND before calling cpu_rng_rdrand(). cpu_earlyrng() checks CPU support of RDSEED and RDRAND before calling cpu_rng_rd

CVS commit: src/sys/arch/x86/x86

2019-11-01 Thread Takahiro Kambe
Module Name:src Committed By: taca Date: Fri Nov 1 15:01:27 UTC 2019 Modified Files: src/sys/arch/x86/x86: cpu_rng.c Log Message: Check CPU support of RDRAND before calling cpu_rng_rdrand(). cpu_earlyrng() checks CPU support of RDSEED and RDRAND before calling cpu_rng_rd

CVS commit: src/sys/arch/x86/x86

2019-10-30 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Wed Oct 30 16:32:04 UTC 2019 Modified Files: src/sys/arch/x86/x86: fpu.c Log Message: Style. To generate a diff of this commit: cvs rdiff -u -r1.58 -r1.59 src/sys/arch/x86/x86/fpu.c Please note that diffs are not public domain; t

CVS commit: src/sys/arch/x86/x86

2019-10-30 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Wed Oct 30 16:32:04 UTC 2019 Modified Files: src/sys/arch/x86/x86: fpu.c Log Message: Style. To generate a diff of this commit: cvs rdiff -u -r1.58 -r1.59 src/sys/arch/x86/x86/fpu.c Please note that diffs are not public domain; t

CVS commit: src/sys/arch/x86/include

2019-10-29 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 30 05:35:36 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: - GMET is not bit 11 but 17. - Add unknown CPUID Fn8000_000a %edx bit 20. To generate a diff of this commit: cvs rdiff -u -r1.155

CVS commit: src/sys/arch/x86/include

2019-10-29 Thread SAITOH Masanobu
Module Name:src Committed By: msaitoh Date: Wed Oct 30 05:35:36 UTC 2019 Modified Files: src/sys/arch/x86/include: specialreg.h Log Message: - GMET is not bit 11 but 17. - Add unknown CPUID Fn8000_000a %edx bit 20. To generate a diff of this commit: cvs rdiff -u -r1.155

CVS commit: src/sys/arch/x86/x86

2019-10-29 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Tue Oct 29 12:39:46 UTC 2019 Modified Files: src/sys/arch/x86/x86: identcpu.c Log Message: Enable XSAVEOPT. To generate a diff of this commit: cvs rdiff -u -r1.97 -r1.98 src/sys/arch/x86/x86/identcpu.c Please note that diffs are

CVS commit: src/sys/arch/x86/x86

2019-10-29 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Tue Oct 29 12:39:46 UTC 2019 Modified Files: src/sys/arch/x86/x86: identcpu.c Log Message: Enable XSAVEOPT. To generate a diff of this commit: cvs rdiff -u -r1.97 -r1.98 src/sys/arch/x86/x86/identcpu.c Please note that diffs are

CVS commit: src/sys/arch/x86/x86

2019-10-21 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Mon Oct 21 10:09:24 UTC 2019 Modified Files: src/sys/arch/x86/x86: identcpu.c Log Message: Call cpu_probe_fpu() only once (from cpu0), and style. To generate a diff of this commit: cvs rdiff -u -r1.96 -r1.97 src/sys/arch/x86/x86/i

CVS commit: src/sys/arch/x86/x86

2019-10-21 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Mon Oct 21 10:09:24 UTC 2019 Modified Files: src/sys/arch/x86/x86: identcpu.c Log Message: Call cpu_probe_fpu() only once (from cpu0), and style. To generate a diff of this commit: cvs rdiff -u -r1.96 -r1.97 src/sys/arch/x86/x86/i

CVS commit: src/sys/arch/x86/x86

2019-10-18 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Oct 18 16:26:38 UTC 2019 Modified Files: src/sys/arch/x86/x86: vm_machdep.c Log Message: Remove unused call to savectx(). To generate a diff of this commit: cvs rdiff -u -r1.38 -r1.39 src/sys/arch/x86/x86/vm_machdep.c Please

CVS commit: src/sys/arch/x86/x86

2019-10-18 Thread Maxime Villard
Module Name:src Committed By: maxv Date: Fri Oct 18 16:26:38 UTC 2019 Modified Files: src/sys/arch/x86/x86: vm_machdep.c Log Message: Remove unused call to savectx(). To generate a diff of this commit: cvs rdiff -u -r1.38 -r1.39 src/sys/arch/x86/x86/vm_machdep.c Please

CVS commit: src/sys/arch/x86/x86

2019-10-18 Thread Juergen Hannken-Illjes
Module Name:src Committed By: hannken Date: Fri Oct 18 14:59:22 UTC 2019 Modified Files: src/sys/arch/x86/x86: multiboot2.c Log Message: Make compile with "options DEBUG". To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/x86/x86/multiboot2.c Plea

CVS commit: src/sys/arch/x86/x86

2019-10-18 Thread Juergen Hannken-Illjes
Module Name:src Committed By: hannken Date: Fri Oct 18 14:59:22 UTC 2019 Modified Files: src/sys/arch/x86/x86: multiboot2.c Log Message: Make compile with "options DEBUG". To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/sys/arch/x86/x86/multiboot2.c Plea

CVS commit: src/sys/arch/x86/x86

2019-10-17 Thread Emmanuel Dreyfus
Module Name:src Committed By: manu Date: Fri Oct 18 00:56:25 UTC 2019 Modified Files: src/sys/arch/x86/x86: efi.c Log Message: Fix EFI system table mapping in virtual space Previous version was annoted as untested, and indeed it did not work. New version uses the same app

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