Add configs:
o CONFIG_SYS_GENERIC_BOARD
o CONFIG_DISPLAY_BOARDINFO
in C29XPCIE config header file to use U-boot generic
board code.
Signed-off-by: Chunhe Lan
---
include/configs/C29XPCIE.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/configs/C29XPCIE.h b/
Add configs:
o CONFIG_SYS_GENERIC_BOARD
o CONFIG_DISPLAY_BOARDINFO
in P1023RDB config header file to use U-boot generic
board code.
Signed-off-by: Chunhe Lan
---
include/configs/P1023RDB.h |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/configs/P1023RDB.h b
From: Tang Yuantian
Signed-off-by: Tang Yuantian
---
include/configs/P1022DS.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 54e2569..de0613f 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -11,6 +11,
In a message from Wolfgang Denk highlighting warnings from cppcheck,
the patch will address those that are correctly diagnosed. Some are
false-positives:
> [fs/zfs/zfs.c:937]: (error) Memory leak: l
dmu_read() allocates "l" if successful, so error-case should not free
it.
> [fs/zfs/zfs.c:1141]: (e
On Wed, 2014-11-05 at 08:08 +0100, Heiko Schocher wrote:
> Hello Scott,
>
> Am 03.11.2014 22:34, schrieb Scott Wood:
> > On Fri, 2014-10-31 at 11:26 +0100, Heiko Schocher wrote:
> >> Add MAINTAINERS and doc/git-mailrc entry.
> >>
> >> Signed-off-by: Heiko Schocher
> >>
> >> ---
> >> as discussed t
IRAM will power off and microcode will lost when system go into
deepsleep, so upload it when resume deepsleep.
Signed-off-by: Zhao Qiang
---
board/freescale/ls1021aqds/ls1021aqds.c | 4 +-
drivers/qe/qe.c | 76 +
drivers/qe/qe.h
Hi,
On 07/11/14 10:55, Hyungwon Hwang wrote:
> This patch adds support for Odroid-XU3.
>
> Signed-off-by: Hyungwon Hwang
> Cc: Minkyu Kang
> Cc: Lukasz Majewski
> ---
> Changes for v3:
> - Remove unnecessary node from DT file
> - Remove unnecessary features from config file
>
Hello Wolfgang,
Am 06.11.2014 16:10, schrieb Wolfgang Denk:
Dear Heiko,
In message<545b81d9.6070...@denx.de> you wrote:
[drivers/mtd/ubi/eba.c:1275]: (error) Uninitialized variable: aeb
can you please have a look? Thanks!
I see in drivers/mtd/ubi/eba.c:
1267:ubi_rb_for_e
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass wrote:
> We should invalidate the TLB right at the start to ensure that we don't get
> false address translations even though paging is disabled.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/start16.S | 3 +++
> 1 file changed, 3 insertions(+)
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass wrote:
> This allows early board init before board_init_f() is called. We already
> have a standard U-Boot board call, and no boards use this, so drop it.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/start.S | 5
Hi all,
I am dealing with some phy devices made by Cortina and the current
U-Boot PHY infrastructure is giving me some huge headaches.
First of all, Cortina does not follow any of the standards for their
phys. Their phys use clause 45 but use device 0 registers 0 and 1 for
the PHY ID instead of t
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass wrote:
> This allows a board to do very early init, but no boards need to do this.
> We may as well drop this feature.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/cpu/start16.S | 10 +-
> 1 file changed, 1 insertion(+), 9 deletions(-)
>
>
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass wrote:
> This was missed when the real mode support was dropped. Remove it.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/config.mk | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/x86/config.mk b/arch/x86/config.mk
> index 3e7fedb..bb2
Hi Bin,
On 6 November 2014 19:12, Bin Meng wrote:
> Hi Simon,
>
> On Fri, Nov 7, 2014 at 9:53 AM, Simon Glass wrote:
>> Hi Bin,
>>
>>
>> On 6 November 2014 18:39, Bin Meng wrote:
>>> Hi Simon,
>>>
>>> On Fri, Nov 7, 2014 at 8:26 AM, Simon Glass wrote:
Hi Bin,
On 6 November
On 4 November 2014 07:58, Bin Meng wrote:
> Return the saved TSC frequency in get_tbclk_mhz().
>
> Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested on link:
Tested-by: Simon Glass
___
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U-Boot@lists.denx.de
http://lists.denx.de
On 4 November 2014 07:58, Bin Meng wrote:
> Use the same way that Linux does for quick TSC calibration via PIT
> when calibration via MSR fails.
>
> Signed-off-by: Bin Meng
Acked-by: Simon Glass
___
U-Boot mailing list
U-Boot@lists.denx.de
http://list
On 4 November 2014 07:58, Bin Meng wrote:
> Using MSR_PLATFORM_INFO (0xCE) to calibrate TSR will cause #GP on
> processors which do not have this MSR. Instead only doing the MSR
> calibration for known/supported CPUs.
>
> Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested on link:
Tested-by:
Hi Bin,
On 6 November 2014 19:22, Simon Glass wrote:
> Hi Bin,
>
> On 4 November 2014 07:58, Bin Meng wrote:
>> Currently only basic CPU information (x86 or x86_64) is displayed
>> on boot. This commit adds more detailed information output including
>> CPU vendor name, device id, family, model a
Hi Bin,
On 4 November 2014 07:58, Bin Meng wrote:
> Currently only basic CPU information (x86 or x86_64) is displayed
> on boot. This commit adds more detailed information output including
> CPU vendor name, device id, family, model and stepping as well as
> the CPU brand string, all of which are
Hi Simon,
On Fri, Nov 7, 2014 at 9:53 AM, Simon Glass wrote:
> Hi Bin,
>
>
> On 6 November 2014 18:39, Bin Meng wrote:
>> Hi Simon,
>>
>> On Fri, Nov 7, 2014 at 8:26 AM, Simon Glass wrote:
>>> Hi Bin,
>>>
>>>
>>> On 6 November 2014 17:07, Bin Meng wrote:
Hi Simon,
> -static struc
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang
Cc: Minkyu Kang
Cc: Lukasz Majewski
---
Changes for v3:
- Remove unnecessary node from DT file
- Remove unnecessary features from config file
- Remove unnecessary macros from board-specific header file
This is v5 of the patchset adding support Odroud XU3 board.
link to the previous version:
v2: https://www.mail-archive.com/u-boot@lists.denx.de/msg152275.html
v3: https://www.mail-archive.com/u-boot%40lists.denx.de/msg152677.html
v4: https://patchwork.ozlabs.org/patch/407411/
This patchset fixes
This patch fixes wrong GPIO information such as GPIO bank, table which
is used to convert GPIO name to index, bank base address, and etc.
Signed-off-by: Hyungwon Hwang
Cc: Minkyu Kang
Cc: Lukasz Majewski
---
Changes for v4:
- None
Changes for v5:
- None
arch/arm/include/asm/arc
Hi Bin,
On 6 November 2014 18:39, Bin Meng wrote:
> Hi Simon,
>
> On Fri, Nov 7, 2014 at 8:26 AM, Simon Glass wrote:
>> Hi Bin,
>>
>>
>> On 6 November 2014 17:07, Bin Meng wrote:
>>> Hi Simon,
>>>
-static struct pci_config_table pci_coreboot_config_table[] = {
+static struct pci_conf
Hi Simon,
On Fri, Nov 7, 2014 at 8:26 AM, Simon Glass wrote:
> Hi Bin,
>
>
> On 6 November 2014 17:07, Bin Meng wrote:
>> Hi Simon,
>>
>>> -static struct pci_config_table pci_coreboot_config_table[] = {
>>> +static struct pci_config_table pci_x86_config_table[] = {
>>> /* vendor, device,
在 11/7/2014 4:20 AM, Marek Vasut 写道:
On Wednesday, November 05, 2014 at 10:18:25 AM, Peng Fan wrote:
在 11/5/2014 5:03 PM, Marek Vasut 写道:
On Wednesday, November 05, 2014 at 07:00:32 AM, Peng Fan wrote:
在 11/5/2014 1:33 AM, Marek Vasut 写道:
On Tuesday, November 04, 2014 at 02:29:56 PM, Peng F
Include a weak function board_usb_phy_mode.
usb_phy_enable decide whether the controller in device mode or in host mode by
'*phy_ctrl & USBPHY_CTRL_OTG_ID'.
There are two usb port on mx6sxsabresd and also mx6slevk.
1. OTG port
2. HOST port
There are connected to SOC USB controller OTG1 core and O
This patch set is mainly to add board level usb support for mx6sxsabresd and
mx6slevk. Add pin mux settings and implement board_ehci_hcd_init and board_usb
_phy_mode.
Also in order to make the host port work for these two boards. A new weak
function is introduced. Detailed info about this is in th
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode
There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core <---> board otg port
otg2 core <---> bo
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode
There are two usb port on mx6sxsabresd board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core <---> board otg port
otg2 core <---
On Wed, 29 Oct 2014 16:03:57 +0100
wrote:
> From: Dirk Eibach
>
> The gdsys hrcon board is based on a Freescale MPC8308 SOC.
> It boots from NOR-Flash, kernel and rootfs are stored on
> SD-Card.
>
> On board peripherals include:
> - 1x GbE (optional)
> - Lattice ECP3 FPGA connected via eLBC an
On Thu, 6 Nov 2014 10:25:58 -0800
York Sun wrote:
> On 11/05/2014 10:29 PM, Dirk Eibach wrote:
> > Hi Stefan,
> >
> >>> Is Kim still active? Last message from him on the list I found was from
> >>> may.
> >>
> >> Not sure. Lets wait and see if Kim responds...
> >
> > looks not so good.
> > I pu
Hi Bin,
On 6 November 2014 17:14, Bin Meng wrote:
> Hi Simon,
>
> On Fri, Nov 7, 2014 at 4:19 AM, Simon Glass wrote:
>> Add some functions to access cpuid from C in various useful ways. Also
>> add a function to get the stack pointer and another to halt the CPU.
>>
>> Signed-off-by: Simon Glass
Hi Bin,
On 6 November 2014 17:07, Bin Meng wrote:
> Hi Simon,
>
> On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass wrote:
>> This code is not really Coreboot-specific, so move it into the common area
>> and rename it.
>
> OK, but current coreboot pci codes are broken, thus need to be fixed
> before
On 11/06/2014 05:40 PM, Anatolij Gustschin wrote:
> Hi Dinh,
>
> On Thu, 6 Nov 2014 17:03:48 -0600
> Dinh Nguyen wrote:
>
>> Hi Marek,
>>
>> Have you been able to successfully boot Linux using the mainline uboot?
>> I cannot seem to be able to boot linux on the C5 SocDK.
>>
>> It starts to boot
Hi Simon,
On Fri, Nov 7, 2014 at 4:19 AM, Simon Glass wrote:
> Add some functions to access cpuid from C in various useful ways. Also
> add a function to get the stack pointer and another to halt the CPU.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/include/asm/processor.h | 121
> +++
With fresh environment the kernel gets wrong console
argument and boots without console output. Fix it.
Reported-by: Dinh Nguyen
Signed-off-by: Anatolij Gustschin
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Marek Vasut
---
include/configs/socfpga_cyclone5.h |2 +-
1 file changed, 1 insertion(
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass wrote:
> This code is not really Coreboot-specific, so move it into the common area
> and rename it.
OK, but current coreboot pci codes are broken, thus need to be fixed
before making it common.
> Signed-off-by: Simon Glass
> ---
>
> arch/
Hi Dinh,
On Thu, 6 Nov 2014 17:03:48 -0600
Dinh Nguyen wrote:
> Hi Marek,
>
> Have you been able to successfully boot Linux using the mainline uboot?
> I cannot seem to be able to boot linux on the C5 SocDK.
>
> It starts to boot linux, but then reboots after a bit back into u-boot.
> So I com
On 11/06/2014 03:54 AM, Wolfgang Denk wrote:
> Hello,
>
> cppcheck reports:
>
> [arch/powerpc/cpu/mpc85xx/cmd_errata.c:62]: (error) Uninitialized variable:
> x108
>
> [board/freescale/common/cds_pci_ft.c:36]: (error) Possible null pointer
> dereference: map
> [board/freescale/common/cds_pci_ft
Hi Marek,
Have you been able to successfully boot Linux using the mainline uboot?
I cannot seem to be able to boot linux on the C5 SocDK.
It starts to boot linux, but then reboots after a bit back into u-boot.
So I commented out #define CONFIG_HW_WATCHDOG in
include/configs/socfpga_cyclone5.h. Th
Hi,
On 20 October 2014 09:51, Przemyslaw Marczak wrote:
>
> Hello,
>
> ... snip ...
>>>
>>>
>>> Thank you again.
>>> I'm going to check the i2c-working tree and maybe rebase the dm-pmic onto
>>> it.
>>>
>>> Is it good idea?
>>
>>
>> Sounds good. Once I get the main DM patches landed (hopefully t
On Thu, 06 Nov 2014 10:00:12 -0700
Stephen Warren wrote:
> On 11/06/2014 03:23 AM, Lukasz Majewski wrote:
> > This change helps to run script on machines with quite long uptime.
> > Without this the following error emerges:
> >
> > File: ./dat_14M.img
> > umount: /mnt/tmp-ums-test: device is busy
On Thu, 6 Nov 2014 21:23:46 +0100
Marek Vasut wrote:
> On Thursday, November 06, 2014 at 10:59:17 AM, Lukasz Majewski wrote:
> > Hi Marek,
> >
> > > Split the Samsung specific PHY control into a separate file
> > > and compile this into the S3C OTG driver only if used on a
> > > Samsung system.
On Thursday, November 06, 2014 at 01:51:51 PM, Soeren Moch wrote:
> Not only skip storage devices with DEV_TYPE_UNKNOWN, but also all devices
> which are unknown to u-boot (e.g., are not HARDDISK, TAPE, CDROM, OPDISK).
>
> This especially avoids long timeouts when probing for external usb
> harddi
This allows a board to do very early init, but no boards need to do this.
We may as well drop this feature.
Signed-off-by: Simon Glass
---
arch/x86/cpu/start16.S | 10 +-
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S
index 6
This code is a little muddled, so tidy it up. Make sure that we put the
GDT in the right place and set it up properly.
Signed-off-by: Simon Glass
---
arch/x86/cpu/start.S | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu
Add support for CAR so that we have memory to use prior to DRAM init.
On link there is a total of 128KB of CAR available, although some is
used for the memory reference code.
Signed-off-by: Simon Glass
---
arch/x86/Kconfig | 16
arch/x86/cpu/ivybridge/car.S | 1
Instead of having an x86-specific DRAM init function, adjust things so we
can use the normal one.
Signed-off-by: Simon Glass
---
arch/x86/cpu/coreboot/sdram.c | 11 ---
arch/x86/include/asm/u-boot-x86.h | 4 ++--
common/board_f.c | 6 +-
3 files changed, 7 ins
On Tuesday, November 04, 2014 at 08:34:21 PM, Pavel Machek wrote:
> On Tue 2014-11-04 06:07:32, Marek Vasut wrote:
> > Split the Samsung specific PHY control into a separate file
> > and compile this into the S3C OTG driver only if used on a
> > Samsung system.
> >
> > Signed-off-by: Marek Vasut
On Tuesday, November 04, 2014 at 08:36:57 PM, Pavel Machek wrote:
> On Tue 2014-11-04 06:07:33, Marek Vasut wrote:
> > Allow passing in a custom configuration of the gusbcfg register
> > via platform data.
> >
> > Signed-off-by: Marek Vasut
> > Cc: Chin Liang See
> > Cc: Dinh Nguyen
> > Cc: Vin
On Thursday, November 06, 2014 at 10:59:17 AM, Lukasz Majewski wrote:
> Hi Marek,
>
> > Split the Samsung specific PHY control into a separate file
> > and compile this into the S3C OTG driver only if used on a
> > Samsung system.
> >
> > Signed-off-by: Marek Vasut
> > Cc: Chin Liang See
> > Cc
Newer Intel chips require a Management Engine which requires a particular
format for the SPI flash that contains the boot loader. Add a tool that
supports creating and modifying these ROM images.
This tool is from Chrome OS but has been cleaned up to use U-Boot style
and to add comments. A few fea
Many of the x86 CONFIG options will be common across different boards. Move
them to a common file.
Signed-off-by: Simon Glass
---
include/configs/coreboot.h | 289 ++-
include/configs/x86-common.h | 272
2 files
When not relying on Coreboot for GPIO init the GPIOs must be set up
correctly. This is currently done statically through a rather ugly method.
As the GPIOs are figured out they can be moved to the device tree and set
up as needed rather than all at the start.
In this implementation, board files sh
Many PCH devices are hard-coded to a particular PCI address. Set these
up early in case they are needed.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c | 142 +
arch/x86/cpu/ivybridg
The local advanced programmable interrupt controller is not used much in
U-Boot but we do need to set it up. Add basic support for this, which will
be extended as needed.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/cpu.c | 3 ++
arch/x86/include/asm/lapic.h | 59 +++
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.
SDRAM init works by setting
The built-in self test value should be checked before we continue booting.
Refuse to continue if there is something wrong.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/cpu.c | 16
1 file changed, 16 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cp
It is convenient to be able to adjust MSRs with a structure that splits the
two 32-bit halves into separate fields, as they are often dealt with
separately. Add a few functions to support this.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/msr.h | 19 +++
1 file changed, 1
Microcode updates are stored in the device tree. Work through these and
apply any that are needed.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c| 5 +
arch/x86/cpu/ivybridge/microcode_intel.c| 1
This function can probably be used on all x86 boards, so move it into the
common file.
Signed-off-by: Simon Glass
---
arch/x86/cpu/coreboot/coreboot.c | 24
arch/x86/cpu/cpu.c | 24
2 files changed, 24 insertions(+), 24 deletions(-
These are available on other architectures. Make them available on x86 also.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/io.h | 49 +++
1 file changed, 49 insertions(+)
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index
Enable GPIO support and provide the required GPIO setup information to
the driver.
Signed-off-by: Simon Glass
---
arch/x86/dts/link.dts | 3 +
board/google/chromebook_link/link.c | 107
include/configs/chromebook_link.h | 4 +-
3 files ch
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.
This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be bo
On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
makes sense for U-Boot to build this image automatically. Unfortunately
it relies on binary blobs so we cannot require this for the default
build as yet.
Add two microcode updates that are provided for this CPU. The updates
have been converted to a device tree form.
(The license needs to be converted to SPDX)
Signed-off-by: Simon Glass
---
arch/x86/dts/link.dts | 10 +
arch/x86/dts/m12206a7_0028.dtsi | 622 +++
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
Enable PCI so we can access devices that need to be set up before relocation.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/cpu.c | 5 +
arch/x86/cpu/pci.c | 31 ++-
arch/x86/include/asm/global_data.h | 1 +
include/configs/chromeb
Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one
for this purpose. Also remove a useless/misleading comment.
Signed-off-by: Simon Glass
---
arch/x86/cpu/coreboot/coreboot.c | 5 +
arch/x86/cpu/cpu.c| 1 -
arch/x86/include/asm/u-boot-x86.h | 1 +
c
Some functions are missing prototypes. Fix those that are specific to x86.
Signed-off-by: Simon Glass
---
arch/x86/cpu/coreboot/coreboot.c | 4 +---
arch/x86/cpu/coreboot/sdram.c | 4 ++--
arch/x86/cpu/cpu.c| 3 +--
arch/x86/cpu/interrupts.c | 2 +-
arch/x86/include
The PCH (Peripheral Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/cpu.c
This allows early board init before board_init_f() is called. We already
have a standard U-Boot board call, and no boards use this, so drop it.
Signed-off-by: Simon Glass
---
arch/x86/cpu/start.S | 5 -
board/chromebook-x86/coreboot/Makefile | 2 +-
board
Set up the flex ratio (controls speed versus heat output) and a few other
very early things.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/cpu.c | 130 ++
arch/x86/include/asm/arch-ivybridge/model_206ax.h | 82 ++
arch/x86/include/as
For board IDs a common approach is to set aside several GPIOs for use in
determining the board ID. This can provide information about board features
and the revision.
Add a function that turns a list of GPIOs into an integer by assigning
each GPIO to a single bit.
Signed-off-by: Simon Glass
---
There is no need to explicitly write 'arch-coreboot' when including headers,
as when the arch directory points to coreboot the correct files will be
used.
Signed-off-by: Simon Glass
---
arch/x86/cpu/coreboot/coreboot.c | 4 ++--
arch/x86/cpu/coreboot/ipchecksum.c | 2 +-
arch/x86/cpu/coreboot
This was missed when the real mode support was dropped. Remove it.
Signed-off-by: Simon Glass
---
arch/x86/config.mk | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/x86/config.mk b/arch/x86/config.mk
index 3e7fedb..bb2da46 100644
--- a/arch/x86/config.mk
+++ b/arch/x86/config.mk
@@ -15,
This is no-longer needed so drop it.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/init_helpers.h | 1 -
common/board_f.c| 5 -
2 files changed, 6 deletions(-)
diff --git a/arch/x86/include/asm/init_helpers.h
b/arch/x86/include/asm/init_helpers.h
index b07887e..f
Sometimes an array can be of variable size up to a maximum. Add a helper
function to decode this.
Signed-off-by: Simon Glass
---
include/fdtdec.h | 16
lib/fdtdec.c | 20
2 files changed, 36 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.
We should invalidate the TLB right at the start to ensure that we don't get
false address translations even though paging is disabled.
Signed-off-by: Simon Glass
---
arch/x86/cpu/start16.S | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/x86/cpu/start16.S b/arch/x86/cpu/start16.S
ind
The built in self test value is available in register eax on start-up. Save
it so that it can be accessed later. Unfortunately we must wait until the
global_data is available before we can do this, so there is a little bit of
shuffling to keep it around.
Signed-off-by: Simon Glass
---
arch/x86/
Add simple PCI access routines for x86 which permit use before relocation.
The normal PCI stack is still used, but for pre-relocation use there can
only ever be a single hose. After relocation, fall back to the normal
access, although even then on x86 machines there is normally only a single
PCI bu
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.
Signed-off-by: Simon Glass
---
arch/x86/cpu/pci.c| 26
For some CPUs, having malloc() available very early is useful. There is no
reason to delay this since early malloc is allocated before board_init_f()
is called.
Move early malloc() init nearer to the start of the init sequence.
Signed-off-by: Simon Glass
---
common/board_f.c | 2 +-
1 file cha
Add some functions to access cpuid from C in various useful ways. Also
add a function to get the stack pointer and another to halt the CPU.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/processor.h | 121 +++
1 file changed, 121 insertions(+)
diff --gi
In general we can't store things in the data section until we have inited
SDRAM. Some platforms allow this (e.g. those with SPL) but some don't. Move
the pointer to global_data so that it will work on all platforms.
Without this fix the serial port will not work prior to relocation with
driver mod
This code is not really Coreboot-specific, so move it into the common area
and rename it.
Signed-off-by: Simon Glass
---
arch/x86/cpu/Makefile | 1 +
arch/x86/cpu/coreboot/Makefile| 1 -
arch/x86/cpu/{coreboot => }/pci.c | 24 +---
3 files changed, 14 inser
At present U-Boot's x86 support requires Coreboot to run first, starting
up the CPU and then setting up SDRAM and video among other tasks. U-Boot
then runs as a payload. Notably U-Boot does not handle the ACPI fun on
x86 where the kernel can call back into the 'BIOS' to perform certain tasks.
This
On Wednesday, November 05, 2014 at 03:11:10 PM, Masahiro Yamada wrote:
> CMD_IAAD (Interrupt on Async Advance Doorbell) is bit 6, not bit 5.
> While we are here, sort the flags.
>
> Signed-off-by: Masahiro Yamada
Nice catch, applied, thanks!
Best regards,
Marek Vasut
___
On Tuesday, November 04, 2014 at 08:17:21 AM, Nobuhiro Iwamatsu wrote:
> Signed-off-by: Nobuhiro Iwamatsu
> CC: Marek Vasut
Applied, thanks!
Best regards,
Marek Vasut
___
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U-Boot@lists.denx.de
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On Wednesday, November 05, 2014 at 10:18:25 AM, Peng Fan wrote:
> 在 11/5/2014 5:03 PM, Marek Vasut 写道:
> > On Wednesday, November 05, 2014 at 07:00:32 AM, Peng Fan wrote:
> >> 在 11/5/2014 1:33 AM, Marek Vasut 写道:
> >>> On Tuesday, November 04, 2014 at 02:29:56 PM, Peng Fan wrote:
> Hi Marek,
>
Thank you for the responses guys, much appreciated. We will look into using
the latest release.
Another question...
Can we still use setenv() in the board file?
Before, we setup environment variables in board_late_intit() with setenv,
but it doesn't seem to work in new u-boot
I also tried it in
Hi,
On 5 November 2014 13:11, Rabin Vincent wrote:
> On Sat, Nov 01, 2014 at 09:12:37AM -0600, Simon Glass wrote:
>> On 29 October 2014 16:21, Rabin Vincent wrote:
>> > + assert(run_command("setenv ut_var '\"'; setenv ut_var2
>> > \"${ut_var}\"", 0) == 0);
>> > + assert(!strcmp(gete
On Thu, Nov 06, 2014 at 07:12:55PM +0100, Wolfgang Denk wrote:
> Dear Tom Rini,
>
> In message <20141106164628.GR24724@bill-the-cat> you wrote:
> >
> > > [net/eth.c:64]: (error) Uninitialized variable: skip_state
> >
> > Dense code, like cmd_ini.c my cppcheck is OK and looking at the code
> > ma
On Thu, Nov 06, 2014 at 07:10:54PM +0100, Wolfgang Denk wrote:
> Dear Tom,
>
> In message <20141106161600.GQ24724@bill-the-cat> you wrote:
> >
> > trini@bill-the-cat:~/work/u-boot/u-boot-ti (master)$ cppcheck --version
> > Cppcheck 1.52
>
> -> cppcheck --version
> Cppcheck 1.63
Ah, OK.
> > tri
Commit 0f605c1501f6 (Start the deprecation process for generic board)
added a run-time warning message. Let's be noisier for non-generic
boards to inform the dead line of the conversion.
This commit intentionally outputs a warning message to stdout.
We still have many unconverted boards. If we p
On 11/05/2014 10:29 PM, Dirk Eibach wrote:
> Hi Stefan,
>
>>> Is Kim still active? Last message from him on the list I found was from
>>> may.
>>
>>
>> Not sure. Lets wait and see if Kim responds...
>
> looks not so good.
> I put Scott and York from Freescale to CC. Maybe they can inquire at
> F
Dear Tom Rini,
In message <20141106164628.GR24724@bill-the-cat> you wrote:
>
> > [net/eth.c:64]: (error) Uninitialized variable: skip_state
>
> Dense code, like cmd_ini.c my cppcheck is OK and looking at the code
> manually I think it's fine too:
> return ((skip_state = getenv(enetvar))
Dear Tom,
In message <20141106161600.GQ24724@bill-the-cat> you wrote:
>
> trini@bill-the-cat:~/work/u-boot/u-boot-ti (master)$ cppcheck --version
> Cppcheck 1.52
-> cppcheck --version
Cppcheck 1.63
> trini@bill-the-cat:~/work/u-boot/u-boot-ti (master)$ cppcheck --force
> --inline-suppr common/
Hi Nikita,
On 6 November 2014 05:23, Nikita Kiryanov wrote:
>
> Hi all,
>
> I've been trying to do some cleanup in common/lcd.c, and noticed some
> unused code:
>
> One is the CONFIG_LCD_BMP_REL8 stuff. This code was added 2 years ago
> in patch 45d7f52511f43b71b623a502fdf31feb905f70a1, and so fa
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