Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Intel N5X SDRAM driver
support. Reserved 4 bits for Intel N5X SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to limited b
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/clock_manager.c | 15 ---
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --
arch/arm/mac
This is the 2cd version of patchset to clean up clock manager code
and store QSPI reference clock in kHz for SOCFPGA SOC64.
This patchset is extracted from "Add Intel Diamond Mesa SoC support" series.
We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device
and we would like to c
Hi Chris,
On 23.03.21 13:35, Priyanka Jain wrote:
-Original Message-
From: U-Boot On Behalf Of Chris Packham
Sent: Wednesday, March 3, 2021 2:30 AM
To: u-boot@lists.denx.de
Cc: York Sun ; Rainer Boschung
; Chris Packham ;
Masahiro Yamada ; Ovidiu Panait
; Patrick Delaunay
; Simon Gla
On 23.03.21 05:14, Simon Glass wrote:
At present some drivers use -ENOSUPP to indicate that an unknown or
unsupported clock is used. Most use -EINVAL, indicating an invalid value,
so convert everything to that.
Signed-off-by: Simon Glass
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
Chang
Hi Ley Foon,
> -Original Message-
> From: Tan, Ley Foon
> Sent: Tuesday, March 23, 2021 6:49 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject
Hi Ley Foon,
> -Original Message-
> From: Tan, Ley Foon
> Sent: Tuesday, March 23, 2021 6:34 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject
Restructure Stratix10 and Agilex handoff code to used by
all SOC64 devices, in preparation to support handoff for
Diamond Mesa.
Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c
which contains the generic function to parse the handoff
data.
Update system_manager_soc64.c to use generic han
Rearrange sequence of macros in handoff_soc64.h without any functionality
change. In preparation for Stratix10 and Agilex handoff function
restructuring.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 22 --
1 file changed, 12 insertions
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile| 4 ++--
.../arm/mach-socfpga/{system_manager_s10.c => system_manager_soc64.c} | 0
2 files changed, 2 inserti
Rename to common file name to used by all SOC64 devices.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile| 4 ++--
.../mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} | 0
2 files changed, 2 insertions(+), 2 deletions(-)
r
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from
S10_HANDOFF to SOC64_HANDOFF.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/clock_manager_s10.c | 2 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 --
arch/arm/mach-socfpga/inc
This is the 2cd version of patchset to restructure Stratix10 and Agilex
handoff code to be generic and to be used by all SOC64 devices.
This patchset is extracted from "Add Intel Diamond Mesa SoC support" series.
We are in preparation to support new Intel N5X (Diamond Mesa) SOC64 device
and we wou
>-Original Message-
>From: U-Boot On Behalf Of Daniel
>Schwierzeck
>Sent: Wednesday, March 17, 2021 3:54 AM
>To: Aleksandar Gerasimovski powergrids.com>; Tom Rini ; u-boot@lists.denx.de;
>Priyanka Jain (OSS)
>Subject: Re: Patches pending for review
>
>Am Montag, den 15.03.2021, 21:24 +
Dear Tom,
Please find my pull-request for u-boot-fsl-qoriq/master
https://github.com/u-boot/u-boot/pull/58
Summary
Bug fixes related to FSL-IFC, watchdog
layerscape-pcie, flexspi, T2080rdb.
priyankajain
-
The following changes since commit 1f9c3f13f6ad8595a0fb5ab2cb830583cdc0b60a:
Merge
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Wednesday, March 24, 2021 11:02 AM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject: RE: [v
Hi Maxime & Pantelis,
I notice that this directory always builds its files even if seemingly
nothing has changed:
LD test/built-in.o
DTC test/overlay/test-fdt-base.dtb
DTB test/overlay/test-fdt-base.dtb.S
AS test/overlay/test-fdt-base.dtb.o
DTC test/overlay/test-fd
Hi Ley Foon,
> -Original Message-
> From: Tan, Ley Foon
> Sent: Tuesday, March 23, 2021 6:04 PM
> To: Lim, Elly Siew Chin ; u-boot@lists.denx.de
> Cc: Marek Vasut ; See, Chin Liang
> ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai
> Subject
Hi Sean,
Thanks for the review. I fix almost of the issues. Will upload the v3 soon.
Still have some questions.
Sean Anderson 於 2021/3/23 下午11:06 寫道:
>
>
>
> if (anatop_reg->supply) {
> ret = regulator_set_value(anatop_reg->supply, uV + 15);
> if (ret)
> retu
Hi Dario,
On Wed, Mar 24, 2021 at 1:27 AM Dario Binacchi wrote:
>
> Hi Bin,
>
> > Il 22/03/2021 02:25 Bin Meng ha scritto:
> >
> >
> > Hi Dario,
> >
> > On Sun, Mar 21, 2021 at 11:19 PM Dario Binacchi wrote:
> > >
> > > Hi Tom,
> > >
> > > > Il 18/03/2021 20:51 Tom Rini ha scritto:
> > > >
> >
On 3/23/21 12:54 PM, Manuel Luís Reis wrote:
Hi again,
There are timers on the board. How come it used to work, before the
commit that breaks it ?
I understand that nobody registers a driver in the UCLASS_TIMER , but
why was this enforced? and if this enforcement breaks our board, we can
eithe
On 3/23/21 4:35 AM, Green Wan wrote:
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual
https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf
On 3/23/21 4:35 AM, Green Wan wrote:
Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
allow different riscv hart perform setup code for each hart as early
as possible. Since all the harts enter the calback, they must be able
nit: callback
to run the same setup.
Signed-of
Commit 69076dff2284 ("cmd: pxe: add support for FDT overlays") added
support for loading DT overlay files to PXE boot. However, it needs
additional environment variable which points to memory location which
can be used to temporary store overlay data.
Add it and in the process unify alignment usin
On 3/23/21 6:08 PM, Manuel Luís Reis wrote:
> Hi again,
>
> FYI: As a small test I commented out the change you mentioned but got
> the same mistake. Begs to wonder if it is
> related to the issue at hand.
>
> Going back to
> http://u-boot.10912.n7.nabble.com/PATCH-v2-time-Fix-get-ticks-being
We are currently not adding any events on the eventlog apart from the
SpecID event. The locality event is mandatory and must be logged before
extending PCR[0].
The spec description is
"The Startup Locality event should be placed in the log before any event
which extends PCR[0]. This allows softwa
Provide a unit test for the longjmp() library function
Signed-off-by: Heinrich Schuchardt
Acked-by: Sean Anderson
---
v3:
check variable on stack
v2:
no change
---
test/lib/Makefile | 1 +
test/lib/longjmp.c | 73 ++
2 files changed,
The implementation of longjmp() is simplified.
A unit test for longjmp() is provided.
For testing use
CONFIG_UNIT_TEST=y
CONFIG_CMD_SETEXPR=n
and execute
ut lib
v3:
improve unit test
v2:
correct title of patch 1
Heinrich Schuchardt (2):
riscv: simplify longjmp
The value returned by setjmp must be nonzero. If zero is passed as
parameter it must be replaced by 1.
This patch reduces the code size a bit.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Sean Anderson
Reviewed-by: Leo Yu-Chi Liang
---
v3:
no change
v2:
correct typo in title
Hi Bin,
> Il 22/03/2021 02:25 Bin Meng ha scritto:
>
>
> Hi Dario,
>
> On Sun, Mar 21, 2021 at 11:19 PM Dario Binacchi wrote:
> >
> > Hi Tom,
> >
> > > Il 18/03/2021 20:51 Tom Rini ha scritto:
> > >
> > >
> > > On Thu, Mar 18, 2021 at 08:27:49AM +0100, Dario Binacchi wrote:
> > > > Hi Bin,
Hi Simon and Alex,
Le 23/03/2021 à 01:56, Simon Glass a écrit :
Hi Alex,
On Tue, 23 Mar 2021 at 04:12, Alex G. wrote:
On 3/22/21 9:27 AM, Philippe REYNES wrote:
Hi all,
Le 11/03/2021 à 00:10, Alex G a écrit :
[snip]
I reach the same issue, my customers are also worried with the actual
si
Hi again,
> There are timers on the board. How come it used to work, before the
> commit that breaks it ?
>
> I understand that nobody registers a driver in the UCLASS_TIMER , but
> why was this enforced? and if this enforcement breaks our board, we can
> either:
> 1/ stop the enforcement
> 2/ com
Hi again,
FYI: As a small test I commented out the change you mentioned but got the
same mistake. Begs to wonder if it is
related to the issue at hand.
Going back to
http://u-boot.10912.n7.nabble.com/PATCH-v2-time-Fix-get-ticks-being-non-monotonic-td426172.html
Sean Anderson asks:
"So nothing
On 3/23/21 1:28 PM, Manuel Luís Reis wrote:
> Hi,
>
> Thanks for your reply.
>
> > Can you please check if this commit is in your tree, or, if the same has
> > to be applied in your case (sama5d3), to make it work ?
>
> I've got that change in my tree, but I'm still getting the error message.
Hi,
Can you please check if this commit is in your tree, or, if the same has
to be applied in your case (sama5d3), to make it work ?
Here is the commit :
https://source.denx.de/u-boot/custodians/u-boot-atmel/-/commit/786f35b619ddbfb88e4532d11a56413f5dab473f
On 3/23/21 1:06 PM, Manuel Luís R
On 3/23/21 9:48 AM, Ying-Chun Liu wrote:
> From: "Ying-Chun Liu (PaulLiu)"
>
> Anatop is an integrated regulator inside i.MX6 SoC.
> There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
> And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
> This patch adds the Anatop
From: "Ying-Chun Liu (PaulLiu)"
Document the bindings for fsl,anatop-regulator
Signed-off-by: Ying-Chun Liu (PaulLiu)
---
.../regulator/fsl,anatop-regulator.txt| 45 +++
1 file changed, 45 insertions(+)
create mode 100644 doc/device-tree-bindings/regulator/fsl,anatop-r
From: "Ying-Chun Liu (PaulLiu)"
Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.
Signed-off-by: Ying-Chun Liu (PaulLi
From: "Ying-Chun Liu (PaulLiu)"
Anatop is an integrated regulator inside i.MX6 SoC.
There are 3 digital regulators which controls PU, CORE (ARM), and SOC.
And 3 analog regulators which controls 1P1, 2P5, 3P0 (USB).
This patch adds the Anatop regulator driver.
Ying-Chun Liu (PaulLiu) (2):
power
On 3/22/21 12:42 PM, Heinrich Schuchardt wrote:
On 22.03.21 14:30, Sean Anderson wrote:
On 3/22/21 9:23 AM, Sean Anderson wrote:
On 3/22/21 7:02 AM, Heinrich Schuchardt wrote:
Provide a unit test for the longjmp() library function
Signed-off-by: Heinrich Schuchardt
---
v2:
no change
-
> The change may be dedicated to sama5d2 devices. Could you have a look
> please if your device (sama5d3) needs this change as well ? I mean, does
> doing something similar for sama5d3 fixes your problem ?
I am not quite sure how to check what you suggest to be honest.
The commit you've sent see
>-Original Message-
>From: U-Boot On Behalf Of Chris Packham
>Sent: Wednesday, March 3, 2021 2:30 AM
>To: u-boot@lists.denx.de
>Cc: York Sun ; Rainer Boschung
>; Chris Packham ;
>Masahiro Yamada ; Ovidiu Panait
>; Patrick Delaunay
>; Simon Glass ; Stefan
>Roese ; Stephen Warren
>Subjec
Hi Heinrich,
On Mon, Mar 22, 2021 at 12:02:48PM +0100, Heinrich Schuchardt wrote:
> The value returned by setjmp must be nonzero. If zero is passed as
> parameter it must be replaced by 1.
>
> This patch reduces the code size a bit.
>
> Signed-off-by: Heinrich Schuchardt
> Sean Anderson
I thi
On RISC-V the symbols __dyn_sym_start, dyn_sym_end are referenced in
efi_runtime_relocate().
Signed-off-by: Heinrich Schuchardt
---
arch/sandbox/cpu/u-boot.lds | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index 936da5e140..a
On Tue, Mar 23, 2021 at 12:01:36AM +0530, Gunjan Gupta wrote:
> Ok...
>
> What about supporting SLC. I dont have a Chip pro, but are you sure that
> the current logic works for that too?
The CHIP Pro has support for the NAND enabled, and if there's an issue
then it should be fixed indeed.
Maxime
Hi,
Thanks for your reply.
> Can you please check if this commit is in your tree, or, if the same has
> to be applied in your case (sama5d3), to make it work ?
I've got that change in my tree, but I'm still getting the error message.
I am using up-to-date mainline U-Boot.
Thanks
On Tue, 23
The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence,
add SPI_NOR_OCTAL_READ flag for this flash.
Signed-off-by: zhengxun
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 2b577
Hello,
I've been having issues with SPL booting in the SAMA5D3 Xplained board
getting the following error, with up-to-date mainline U-boot and
sama5d3_xplained _mmc_defconfig:
---
RomBOOT
Could not initialize timer (err -19)
.
The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence,
add SPI_NOR_OCTAL_READ flag for this flash.
Signed-off-by: zhengxun
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 2b577
Hi Andy,
On 3/18/21 10:59 AM, andy...@sony.com wrote:
Hi
I don't want to revert this commit. Is there any issue without this?
Without revert commit 17ea3c86, Some board, like Dragonboard 410c will meet
transfer data timeout error (we used v2018.01):
U-Boot 2018.01 (Nov 26 2020 - 03:31:09 +00
Hi Neil,
On 2021/3/22 17:18, Neil Armstrong wrote:
With the introduction of pcie_dw_rockchip, and need to support the DW PCIe in
the
Amlogic AXG & G12 SoCs, most of the DW PCIe helpers would be duplicated.
This introduce a "common" DW PCIe helpers file with common code merged from the
dw_ti an
This patch adds an implementation of exec_op, which support octal
mode and quad mode for reading flash and support existing single
mode for reading and writing flash concurrently.
Signed-off-by: zhengxun
---
drivers/spi/renesas_rpc_spi.c | 144 ++
1 file changed,
Hi,
Just a gentle ping.
On Thu, Mar 11, 2021 at 2:44 PM wrote:
>
> From: dillon min
>
> These patches aim to adds u-boot support on art-pi board.
>
> the board resources:
> - stm32h750xbh6 128k flash, 1024k sram
> - 32MiB sdram
> - 16MiB spi flash
> - 8MiB qspi flash
> - onboard wifi, bt, fm
>
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 15, 2021 10:37 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 15, 2021 10:37 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 15, 2021 5:43 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
Fix copy/paste errors in the descriptions of mtrr_close () and mtrr_set().
Signed-off-by: Wolfgang Wallner
---
arch/x86/include/asm/mtrr.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index 3a98aacdef..384672e
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 15, 2021 5:43 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 15, 2021 5:43 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 15, 2021 5:43 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
An entry is missing in the FSP-S devicetree bindings, and as a result
the description for the next few following entries is off by one line.
Signed-off-by: Wolfgang Wallner
---
.../fsp/fsp2/apollolake/fsp-s.txt | 19 ++-
1 file changed, 10 insertions(+), 9 deletions
Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual
https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf
Signed-off-by: Green Wan
---
board/si
Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
allow different riscv hart perform setup code for each hart as early
as possible. Since all the harts enter the calback, they must be able
to run the same setup.
Signed-off-by: Green Wan
---
arch/riscv/cpu/start.S | 5 +
a
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 15, 2021 5:43 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
> -Original Message-
> From: Lim, Elly Siew Chin
> Sent: Monday, March 15, 2021 3:59 PM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Tan, Ley Foon
> ; See, Chin Liang ;
> Simon Goldschmidt ; Chee, Tien Fong
> ; Westergreen, Dalon
> ; Simon Glass ; Gan,
> Yau Wai ; Lim, Elly Siew Chin
Hi Green,
On 23/03/2021 05:36, Green Wan wrote:
> Hi Neil,
>
> pcie_dw_common.* is a good starting point. I'd like to spend time on this.
> Please add me into the loop. Thanks.
Sure, I'll CC you on the next revision, in the meantime don't hesitate to
comment and/or post the changes
needed for
Hi Tom
Please pull one fix for v2021.04-rc5.
Thanks.
Regards
Ley Foon
The following changes since commit 1f9c3f13f6ad8595a0fb5ab2cb830583cdc0b60a:
Merge tag 'efi-2021-04-rc5-2' of
https://source.denx.de/u-boot/custodians/u-boot-efi (2021-03-20 08:55:18 -0400)
are available in the Git repos
On Tue, Mar 23, 2021 at 1:07 PM Bin Meng wrote:
> Hi Green,
>
> On Tue, Mar 23, 2021 at 12:12 PM Green Wan wrote:
> >
> > Hi Bin,
> >
> > I can move it to the place right after stacks for harts are set up and
> right before picking up the lottery hart. (like below) How about the
> function name?
Hi Simon,
On 23/03/21 6:26 am, Simon Glass wrote:
> Hi Kishon,
>
> On Mon, 22 Mar 2021 at 18:11, Kishon Vijay Abraham I wrote:
>>
>> Hi Simon,
>>
>> On 12/03/21 10:15 am, Simon Glass wrote:
>>> Hi Kishon,
>>>
>>> On Tue, 9 Mar 2021 at 05:27, Kishon Vijay Abraham I wrote:
From: Jean-Ja
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