On 3/15/22 7:54 PM, Andre Przywara wrote:
> Commit f11513d99787 ("net: phy: realtek: Add tx/rx delay config for
> 8211e") made the Realtek PHY driver honour the phy-mode DT property,
> to set up the proper delay scheme for the RX and TX lines. A similar
> change in the kernel revealed that those
Now that mkimage can generate TOC0 images, and the SPL can interpret
them, hook up the build infrastructure so the user can choose which
image type to build. Since the absolute load address is stored in the
TOC0 header, that information must be passed to mkimage.
Signed-off-by: Samuel Holland
Most Allwinner sunxi SoCs have separate boot ROMs in non-secure and
secure mode. The "non-secure" or "normal" boot ROM (NBROM) uses the
existing sunxi_egon image type. The secure boot ROM (SBROM) uses a
completely different image type, known as TOC0.
A TOC0 image is composed of a header and two
SPL uses the image header to detect the boot device and to find the
offset of the next U-Boot stage. Since this information is stored
differently in the eGON and TOC0 image headers, add code to find the
correct value based on the image type currently in use.
Signed-off-by: Samuel Holland
---
This series adds support for the TOC0 image format used by the Allwinner
secure boot ROM (SBROM). This series has been tested on the following
SoCs/boards, with the eFuse burnt to enable secure mode:
- A50: Ainol Q88 Tablet
- A64: Pine A64 Plus
- H5: Orange Pi Zero Plus
- H6: Pine H64 Model B
Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.
This also has the added benefit of
Chips attached to the RSB bus require an initialization command before
they can be used. (Specifically, this command programs the chip's
runtime address.) The driver does this in its .probe_chip hook, under
the assumption that .probe_chip is called during child probe. This is
not the case;
Currently, clock/reset setup for this device is handled by a
platform-specific function and is intermixed with non-DM pinctrl
setup. Use the devicetree to get clocks/resets, which disentagles
it from the pinctrl setup in preparation for moving to DM_PINCTRL.
Signed-off-by: Samuel Holland
---
Chips attached to the P2WI bus require an initialization command before
they can be used. (Specifically, this switches the chip from I2C mode
to P2WI mode.) The driver does this in its .probe_chip hook, under the
assumption that .probe_chip is called during child probe. This is not
the case;
A while back, the sunxi-specific P2WI and RSB drivers were converted to
support DM_I2C. Now they are used as non-DM drivers in SPL, and DM
drivers in U-Boot proper.
However, the DM version of the code did not fully initialize either the
controller or the connected chips. So the DM driver would
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.
Signed-off-by: Stanley Chu
---
v2:
- drop the WDnRCRB/CORSTCB register access, it is not for
GPIO modules reset control
---
drivers/pinctrl/Kconfig |1 +
drivers/pinctrl/Makefile |1 +
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/spi/spi-sunxi.c | 84 -
1 file changed, 84 deletions(-)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland
---
(no changes since v1)
arch/arm/include/asm/arch-sunxi/gpio.h | 1 -
drivers/pwm/sunxi_pwm.c| 11 ---
2 files changed, 12 deletions(-)
diff --git
This is the only possible mux setting for the A64's PWM peripheral.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland
---
(no changes since v1)
board/sunxi/board.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 77ceefdb46..9a18399294 100644
---
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 54 +++
1 file changed, 54 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.
Clean up the code in the process: remove #ifdefs and recognize that the
pin configuration is the same for all sun8i/sun50i SoCs, not just those
which select CONFIG_MACH_SUN8I.
When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/i2c/sun6i_p2wi.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
This is now handled automatically by the clock and pinctrl drivers.
SPL still calls this function because it needes the non-DM code.
Signed-off-by: Samuel Holland
---
(no changes since v1)
board/sunxi/board.c | 8
1 file changed, 8 deletions(-)
diff --git a/board/sunxi/board.c
These options are not currently enabled anywhere. Any new users should
use DM clocks and pinctrl.
Signed-off-by: Samuel Holland
---
(no changes since v1)
arch/arm/include/asm/arch-sunxi/gpio.h | 8 -
arch/arm/include/asm/arch-sunxi/i2c.h | 11 +-
arch/arm/mach-sunxi/Kconfig
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/net/sun8i_emac.c | 90
1 file changed, 90 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index
Where multiple options were available, the one matching board.c and the
device trees was chosen.
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 37 +++
1 file
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland
---
(no changes since v1)
arch/arm/include/asm/arch-sunxi/gpio.h | 2 -
board/sunxi/gmac.c | 55 --
2 files changed, 57 deletions(-)
diff --git
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland
---
(no changes since v1)
arch/arm/include/asm/arch-sunxi/gpio.h | 1 -
drivers/net/sunxi_emac.c | 7 +--
2 files changed, 1 insertion(+), 7 deletions(-)
diff --git
This includes UART0 and R_UART (s_uart) on all supported platforms, plus
the additional UART configurations from arch/arm/mach-sunxi/board.c.
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland
---
(no changes since v1)
When a pinctrl driver is available, it will take care of setting up
these pins. However, for now this code is still needed in SPL.
Reviewed-by: Simon Glass
Signed-off-by: Samuel Holland
---
(no changes since v1)
arch/arm/mach-sunxi/board.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
The sunxi pinctrl hardware has bias and drive control. Add driver
support for configuring those options.
Reviewed-by: Simon Glass
Signed-off-by: Samuel Holland
---
(no changes since v1)
drivers/pinctrl/sunxi/Kconfig | 1 +
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 53
Create a do-nothing driver for each sunxi pin controller variant.
Since only one driver can automatically bind to a DT node, since the
GPIO driver already requires a manual binding process, and since the
pinctrl driver needs access to some of the same information, refactor
the GPIO driver to be
The pinmux command uses this function to display pinmux status.
Since the driver cannot map pin numbers to a list of supported
functions, only functions which are common across all pins can be
reported by name.
Signed-off-by: Samuel Holland
---
(no changes since v1)
Implement the operations to get pin and function names, and to set the
mux for a pin. The pin count and pin names are calculated as if each
bank has the maximum number of pins. Function names are simply the index
into a list of { function name, mux value } pairs.
We assume all pins associated
This series resolves some longstanding TODOs by implementing a pinctrl
driver for sunxi platforms and converting DM drivers to use it.
Changes in v2:
- Merge all SoC drivers into one file and one U_BOOT_DRIVER.
- Add a consumer for the APB bus clock
- Add support for the F1C100s SoC
Samuel
Hi Stefan & Hajo,
Please see my comment below.
On Wed, Mar 9, 2022 at 2:44 PM Tony Dinh wrote:
>
> Hi Hajo,
>
> Please see comments below.
>
> On Wed, Mar 9, 2022 at 5:42 AM Hajo Noerenberg
> wrote:
> >
> > On 09.03.2022 at 12:26 Tony Dinh wrote:
> > > Hi Hajo,
> > >
> >
> > Hi Tony,
> >
> >
On 3/17/22 3:14 PM, Heiko Thiery wrote:
Hi Sean,
Am Do., 17. März 2022 um 15:38 Uhr schrieb Sean Anderson :
Hi Heiko,
On 3/17/22 8:41 AM, Heiko Thiery wrote:
With the clock driver enabled for the imx8mq, it was noticed that the
frequency used to calculate the baud rate is always taken from
On 3/17/22 10:47 AM, Michael Walle wrote:
+ struct clk clk;
+ if(!clk_get_by_name(dev, "ipg", ))
+ rate = clk_get_rate();
+ }
+
+ /* as fallback we try to get the clk rate that way */
+ if (rate == 0)
!rate || IS_ERR_VALUE(rate)
This looked so weird I had
On Wed, Mar 16, 2022 at 05:42:32PM +0100, Michal Simek wrote:
> Hi Tom,
>
> please pull these patches to your next branch.
> CI doesn't show any issue.
> https://source.denx.de/u-boot/custodians/u-boot-microblaze/-/pipelines/11311
>
> There are couple of enhancements but also new pinctrl driver
March 17, 2022 1:51 PM, "Alex" wrote:
> Hello!
>
> Running into a potential regression on the SiFive Unmatched.
>
> All SD cards provisioned using identical known-good steps documented by
> u-boot.
Please ignore. I was down to bisecting with multiple gcc toolchains building
u-boot
when I
Adding the SiFive Unmatched maintainers on Cc.
On Thu, Mar 17, 2022 at 3:51 PM Alex wrote:
>
> Hello!
>
> Running into a potential regression on the SiFive Unmatched.
>
> These images function as expected: (u-boot Nov 2021, OpenSPI 0.9)
>
Hi Sean,
Am Do., 17. März 2022 um 15:38 Uhr schrieb Sean Anderson :
>
> Hi Heiko,
>
> On 3/17/22 8:41 AM, Heiko Thiery wrote:
> > With the clock driver enabled for the imx8mq, it was noticed that the
> > frequency used to calculate the baud rate is always taken from the root
> > clock of UART1.
On Wed, Mar 16, 2022 at 5:40 PM Pierre-Clément Tosi wrote:
>
> Swap the arguments as that seems to have been the author's intention.
>
> Note: This fix wasn't tested on hardware and will result in more bits
> being set by the underlying writel() in rk_clrsetreg(), which
> might bring
Hello!
Running into a potential regression on the SiFive Unmatched.
These images function as expected: (u-boot Nov 2021, OpenSPI 0.9)
https://github.com/haiku/firmware/tree/73e14d53b45a6b74/u-boot/riscv64/unmatched
UART output, no issues.
The latest master u-boot images no longer boot from
The Linux kernel moved dt-bindings/pinctrl/pins-imxrt to the device tree
This patch move it in U-Boot as well.
Signed-off-by: Jesse Taube
---
arch/arm/dts/imxrt1020-evk.dts | 2 +-
.../pins-imxrt1020.h => arch/arm/dts/imxrt1020-pinfunc.h| 0
1M of heap is more than internal ram making booting without SDRAM not
possible now it is 256k
Signed-off-by: Jesse Taube
---
configs/imxrt1020-evk_defconfig | 2 +-
configs/imxrt1050-evk_defconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
If FALCON mode is enabled we have a missing include in spl_start_uboot.
Signed-off-by: Jesse Taube
---
board/freescale/imxrt1020-evk/imxrt1020-evk.c | 1 +
board/freescale/imxrt1050-evk/imxrt1050-evk.c | 1 +
2 files changed, 2 insertions(+)
diff --git
In Linux IMX and IMXRT use the device tree to hold the anatop address.
The anatop is used in clock drivers as it controls the internal PLLs
This will move the macro from asm/arch-imxrt to the device tree.
This presumably should also be done with the other IMX boards as well.
Signed-off-by: Jesse
Add binding header for i.MXRT1170 pinctrl device tree.
Signed-off-by: Jesse Taube
---
arch/arm/dts/imxrt1170-pinfunc.h | 1561 ++
1 file changed, 1561 insertions(+)
create mode 100644 arch/arm/dts/imxrt1170-pinfunc.h
diff --git a/arch/arm/dts/imxrt1170-pinfunc.h
Updates to the imxrt family include:
- Adding missing include in board
- Moving pinctrl binding to dts
- Reducing SYS_MALLOC_LEN
- Using device tree for anatop base address
Jesse Taube (4):
clk: imxrt: Use dts for anatop base address
configs/*imxrt10*: SYS_MALLOC_LEN is too large
ARM: dts:
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and Cortex-M4 core.
The EVK provides 64 MB SDRAM, Micro SD card socket,
USB 2.0 OTG.
This patch aims to support the preliminary booting up
Add a base defconfig for the i.MXRT1170
Signed-off-by: Jesse Taube
---
configs/imxrt1170-evk_defconfig | 67 +
include/configs/imxrt1170-evk.h | 37 ++
2 files changed, 104 insertions(+)
create mode 100644 configs/imxrt1170-evk_defconfig
create
The i.MXRT11 series has different offsets for IOCR_MUX, it also can
address 64MiB of SDRAM so add a macro for that.
Signed-off-by: Jesse Taube
---
drivers/ram/imxrt_sdram.c| 9 +
include/dt-bindings/memory/imxrt-sdram.h | 1 +
2 files changed, 10 insertions(+)
diff
The i.MXRT11 series has two new pll types but are variants of existing.
This patch adds the ability to read one of the pll types' frequency
as it can't be changed unlike the generic pll it also has the
division factors swapped.
Signed-off-by: Jesse Taube
---
drivers/clk/imx/clk-pllv3.c | 44
Add clock driver support for i.MXRT1170.
Signed-off-by: Jesse Taube
---
drivers/clk/imx/Kconfig | 16 +++
drivers/clk/imx/Makefile| 1 +
drivers/clk/imx/clk-imxrt1170.c | 215
3 files changed, 232 insertions(+)
create mode 100644
Add the clock binding doc for i.MXRT1170.
Signed-off-by: Jesse Taube
---
include/dt-bindings/clock/imxrt1170-clock.h | 48 +
1 file changed, 48 insertions(+)
create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h
diff --git
This commit adds board support for i.MXRT1170-EVK from NXP. This board
is an evaluation kit provided by NXP for i.MXRT117x processor family.
Signed-off-by: Jesse Taube
---
arch/arm/include/asm/arch-imx/cpu.h | 1 +
arch/arm/mach-imx/imxrt/Kconfig | 9 +++
This patchset contains:
- i.MXRT1170 clock driver adaption
- i.MXRT1170-evk basic support
Jesse Taube (8):
imx: imxrt1170-evk: Add support for the NXP i.MXRT1170-EVK
ARM: dts: imxrt11170-pinfunc: Add pinctrl binding header
dt-bindings: imx: Add clock binding for i.MXRT1170
clk: imx: Add
Add clocks support for the PWM controllers. This is ported from
Linux v5.17-rc8.
Signed-off-by: Tommaso Merciai
---
drivers/clk/imx/clk-imx8mm.c | 28
1 file changed, 28 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index
The current address being read from dt actually represents the ddrss_ctl
memory region, while ddrss_ss region is something else. Introduce
ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper
purpose later so that we can avoid confusion.
Signed-off-by: Dave Gerlach
---
Add CONFIG_NR_DRAM_BANKS from am64x_evm_a53_defconfig as this is needed
to calculate the size of DDR that is available.
Signed-off-by: Dave Gerlach
---
configs/am64x_evm_r5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/am64x_evm_r5_defconfig
Call into k3-ddrss driver to fixup device tree and resize the available
amount of DDR if ECC is enabled.
A second fixup is required from A53 SPL to take the fixup as done from
R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes
this to the OS.
Signed-off-by: Dave Gerlach
---
Use the appropriate fdtdec_setup_mem_size_base and
fdtdec_setup_bank_size calls in dram_init and dram_bank_init to pull
these values from DT, where they are already available, instead of
hardcoding them.
Signed-off-by: Dave Gerlach
---
board/ti/am64x/evm.c | 19 ---
1 file
Add DT binding documentation for enabling ECC in the DDR sub system present
on AM64 device.
Signed-off-by: Dave Gerlach
---
.../memory-controller/k3-j721e-ddrss.txt | 8
1 file changed, 8 insertions(+)
diff --git
Add 'ss_cfg' memory region for memorycontroller node which is required
to enable ECC.
Signed-off-by: Dave Gerlach
---
arch/arm/dts/k3-am64-ddr.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/k3-am64-ddr.dtsi b/arch/arm/dts/k3-am64-ddr.dtsi
index
Introduce ECC Functionality for full memory space as implemented in the
DDRSS. The following is done to accomplish this:
* Introduce a memory region "ss" to allow dt to provide DDRSS region,
which is not the same as "ctl" which is the controller region.
* Introduce a "ti,ecc-enable" flag
Hi,
This series adds support for single bit ECC in the TI DDRSS bridge
inline ECC and adds required support code for AM64x EVM to enable it for
the full DDR space. This ECC module checks reads and writes to and from
DDR once enabled without additional action required. ECC is stored
together with
Hi Sean,
> Hi Heiko,
>
> On 3/17/22 8:41 AM, Heiko Thiery wrote:
> > With the clock driver enabled for the imx8mq, it was noticed that
> > the frequency used to calculate the baud rate is always taken from
> > the root clock of UART1. This can cause problems if UART1 is not
> > used as console
On 3/17/22 16:13, Tommaso Merciai wrote:
On Thu, Mar 17, 2022 at 01:38:18PM +0100, Tommaso Merciai wrote:
On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
On 3/17/22 08:39, Tommaso Merciai wrote:
On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
On 3/16/22 16:27,
On Thu, Mar 17, 2022 at 01:38:18PM +0100, Tommaso Merciai wrote:
> On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
> > On 3/17/22 08:39, Tommaso Merciai wrote:
> > > On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
> > > > On 3/16/22 16:27, Tommaso Merciai wrote:
> > > > >
+ struct clk clk;
+ if(!clk_get_by_name(dev, "ipg", ))
+ rate = clk_get_rate();
+ }
+
+ /* as fallback we try to get the clk rate that way */
+ if (rate == 0)
!rate || IS_ERR_VALUE(rate)
This looked so weird I had to
Hi Heiko,
On 3/17/22 8:41 AM, Heiko Thiery wrote:
With the clock driver enabled for the imx8mq, it was noticed that the
frequency used to calculate the baud rate is always taken from the root
clock of UART1. This can cause problems if UART1 is not used as console
and the settings are different
Versal can also have reserved space in DT which u-boot has to avoid to
placing self to that location. The same change was done in ZynqMP by commit
ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location")
and also for microblaze by commit d7b5cc89d329 ("microblaze: Do not place
Hi Han,
Am 17.03.22 um 14:33 schrieb Han Xu:
>
>
> On Thu, Mar 17, 2022 at 8:27 AM Frieder Schrempf
> mailto:frieder.schre...@kontron.de>> wrote:
>
> Hi Stefano,
>
> this old patch was delegated to you in patchwork. If you're not the
> correct maintainer to address, please let me
On Thu, Mar 17, 2022 at 8:27 AM Frieder Schrempf <
frieder.schre...@kontron.de> wrote:
> Hi Stefano,
>
> this old patch was delegated to you in patchwork. If you're not the
> correct maintainer to address, please let me know. As the NAND layer
> seems to be unmaintained at the moment, I'm not
Hi Stefano,
this old patch was delegated to you in patchwork. If you're not the
correct maintainer to address, please let me know. As the NAND layer
seems to be unmaintained at the moment, I'm not sure whom to ask.
This patch fixes a regression that was introduced by 616f03dabacb ("
mtd: gpmi:
Hi Sean,
Am 17.03.22 um 14:14 schrieb Sean Nyekjaer:
> [Sie erhalten nicht oft E-Mail von "s...@geanix.com". Weitere Informationen,
> warum dies wichtig ist, finden Sie unter
> "http://aka.ms/LearnAboutSenderIdentification;.]
>
> Hi Frieder,
>
> On Thu, Mar 17, 2022 at 01:59:07PM +0100,
Hi Heiko,
On 2022-03-17 05:41, Heiko Thiery wrote:
With the clock driver enabled for the imx8mq, it was noticed that the
frequency used to calculate the baud rate is always taken from the root
clock of UART1. This can cause problems if UART1 is not used as console
and the settings are different
Hi Frieder,
On Thu, Mar 17, 2022 at 01:59:07PM +0100, Frieder Schrempf wrote:
> Am 17.03.22 um 09:06 schrieb Frieder Schrempf:
> > Hi Tim,
> >
> > Am 16.03.22 um 17:34 schrieb Tim Harvey:
> >> On Wed, Mar 16, 2022 at 7:09 AM Fabio Estevam wrote:
> >>>
> >>> Adding Han Xu's NXP email on Cc.
>
From: Marek Behún
Currently we require PHY interface mode to be known when
finding/creating the PHY - the functions
* phy_device_create()
* create_phy_by_mask()
* search_for_existing_phy()
* get_phy_device_by_mask()
* phy_find_by_mask() (this is the only one global)
all require the
Am 17.03.22 um 09:06 schrieb Frieder Schrempf:
> Hi Tim,
>
> Am 16.03.22 um 17:34 schrieb Tim Harvey:
>> On Wed, Mar 16, 2022 at 7:09 AM Fabio Estevam wrote:
>>>
>>> Adding Han Xu's NXP email on Cc.
>>>
>>> On Mon, Mar 14, 2022 at 10:31 AM Frieder Schrempf
>>> wrote:
Hello everyone,
From: Marek Behún
Use phydev->is_c45 instead of is_10g_interface(phydev->interface) to
determine whether clause 45 protocol should be used.
Signed-off-by: Marek Behún
---
drivers/net/phy/phy.c | 8
include/phy.h | 12
2 files changed, 4 insertions(+), 16
From: Marek Behún
Rename constant PHY_INTERFACE_MODE_NONE to PHY_INTERFACE_MODE_NA to make
it compatible with Linux' naming.
Signed-off-by: Marek Behún
---
board/freescale/corenet_ds/eth_hydra.c | 2 +-
board/freescale/corenet_ds/eth_superhydra.c | 4 ++--
From: Marek Behún
We want to be able to have phydev->interface uninitialized during
->probe(). We should assume that phydev->interface is initialized only
before ->config().
Signed-off-by: Marek Behún
---
drivers/net/phy/xilinx_gmii2rgmii.c | 10 +-
1 file changed, 5 insertions(+), 5
From: Marek Behún
Add helpers ofnode_get_phy_node() and dev_get_phy_node() and use it in
net/mdio-uclass.c function dm_eth_connect_phy_handle().
This is useful because other part's of U-Boot may want to get PHY ofnode
without connecting a PHY.
Signed-off-by: Marek Behún
---
From: Marek Behún
The bcmgenet and sun8i_emac drivers call phy_connect(), which finds /
creates the PHY and also connects it to the eth device via
phy_connect_dev(), then set some phydev members (bcmgenet only), and
then call phy_connect_dev() explicitly again.
Drop the second
From: Marek Behún
Move PHY_INTERFACE_MODE_NA to the beginning of the enum definition to
make it have zero value. This makes it possible (although not
encouraged) to test for invalid/nonexistent interface mode with !val
instead of val == PHY_INTERFACE_MODE_NA.
The comment near the definition
From: Marek Behún
Add helpers ofnode_read_phy_mode() and dev_read_phy_mode() to parse the
"phy-mode" / "phy-connection-type" property.
Use them treewide.
This allows us to inline the phy_get_interface_by_name() into
ofnode_read_phy_mode(), since the former is not used anymore.
Signed-off-by:
From: Marek Behún
Rename constant PHY_INTERFACE_MODE_COUNT to PHY_INTERFACE_MODE_MAX to
make it compatible with Linux' naming.
Signed-off-by: Marek Behún
---
drivers/core/ofnode.c | 2 +-
drivers/net/phy/aquantia.c | 2 +-
include/phy_interface.h| 2 +-
3 files changed, 3
From: Marek Behún
The "phy-interface-type" property should be "phy-connection-type".
Signed-off-by: Marek Behún
---
drivers/net/phy/phy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index c9fc20855b..fe6dbdaee4 100644
---
From: Marek Behún
Use the new dm_mdio_read/write/reset() wrappers treewide, instead of
always getting and dereferencing MDIO operations structure pointer.
Signed-off-by: Marek Behún
---
drivers/net/mdio_mux_sandbox.c | 6 ++
net/mdio-mux-uclass.c | 16
From: Marek Behún
Add wrappers dm_mdio_read(), dm_mdio_write() and dm_mdio_reset() for
DM MDIO's .read(), .write() and .reset() operations.
Signed-off-by: Marek Behún
---
include/miiphy.h | 31 +++
net/mdio-uclass.c | 31 +++
2 files
From: Marek Behún
These global variables should both have type
static const char * const
Signed-off-by: Marek Behún
---
net/mdio-uclass.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c
index e74e34f78f..5735afe49e 100644
From: Marek Behún
Use the ARRAY_SIZE() macro instead of hardcoding sizes of arrays in
macors.
Signed-off-by: Marek Behún
---
net/mdio-uclass.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c
index 5735afe49e..649dc60f73
From: Marek Behún
So I wanted to solve a problem regarding MDIO bus within mvneta driver,
to make it use the mvmdio DM driver instead of the non-DM MDIO bus
registered during mvneta probe, and improve some other things there, and
it seems like I opened a small bag from hell, which resulted in
On 3/17/22 13:38, Tommaso Merciai wrote:
On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
On 3/17/22 08:39, Tommaso Merciai wrote:
On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
On 3/16/22 16:27, Tommaso Merciai wrote:
Add function enable_pwm_clk into in
With the clock driver enabled for the imx8mq, it was noticed that the
frequency used to calculate the baud rate is always taken from the root
clock of UART1. This can cause problems if UART1 is not used as console
and the settings are different from UART1. The result is that the console
output is
On Thu, Mar 17, 2022 at 07:55:40AM -0300, Fabio Estevam wrote:
> Hi Tommaso,
>
> On Thu, Mar 17, 2022 at 4:34 AM Tommaso Merciai
> wrote:
>
> > Hi Fabio,
> > You mean is better to move the clock enable into board_late_init function?
>
> Yes, you would only need PWM support in U-Boot proper,
On Thu, Mar 17, 2022 at 12:58:31PM +0100, Marek Vasut wrote:
> On 3/17/22 08:39, Tommaso Merciai wrote:
> > On Wed, Mar 16, 2022 at 09:54:34PM +0100, Marek Vasut wrote:
> > > On 3/16/22 16:27, Tommaso Merciai wrote:
> > > > Add function enable_pwm_clk into in clock_imx8mm.c. This
> > > > function
Hello Michael
A gentle reminder!!
As you said earlier, can you test the mamoj board with proposed solution to fix
SPL size issue.
Regards
Gaurav Jain
> -Original Message-
> From: Gaurav Jain
> Sent: Monday, March 14, 2022 11:18 AM
> To: Michael Nazzareno Trimarchi ; Stefano
> Babic
>
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