The KConfig file was updated to indicate support for am57xx SoCs.
Logic was added to the pruss driver to enable the clock for am57xx pruss
during the driver probe function.
This patch depends on patches 0001 and 0004 of this patch series.
Signed-off-by: Greg Leonberg
---
Added the pruss subsystem to the device tree based on the device tree info
from the Linux kernel.
Signed-off-by: Greg Leonberg
---
arch/arm/dts/dra7.dtsi | 198 +
1 file changed, 198 insertions(+)
diff --git a/arch/arm/dts/dra7.dtsi
In order to support the am33xx pru_rproc, the KConfig needed to have the
depends updated to support either ARCH_K3 or ARCH_OMAP2PLUS. The Makefile
needed to be tweaked because when building for am33xx, the SPL will not fit
into SRAM if the pru_rproc driver is built into it.
The pru_rproc struct
Added the pruss subsystem to the device tree based on the device tree info
from the Linux kernel.
Signed-off-by: Greg Leonberg
---
arch/arm/dts/am33xx.dtsi | 105 +++
1 file changed, 105 insertions(+)
diff --git a/arch/arm/dts/am33xx.dtsi
An integer flag in the private data structure for the udev was added to
indicate run-state. A function was also added to return that flag in order
for the driver to support the is_running driver function.
This patch depends on patch 0007 of this patch series.
Signed-off-by: Greg Leonberg
---
The am57xx pru uses the same logic as the am33xx so it just needed to have
the struct udevice_id updated.
This patch depends on patch 0006 of this patch series.
Signed-off-by: Greg Leonberg
---
drivers/remoteproc/pru_rproc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
The PRM_PER structure needs to be defined in order to allow the pruss
driver to bring the pru subsystem out of reset during the pruss
driver probe
Signed-off-by: Greg Leonberg
---
arch/arm/include/asm/arch-am33xx/cpu.h | 7 +++
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h
In order to support the am33xx pruss, the KConfig needed to have the
depends updated to support either ARCH_K3 or ARCH_OMAP2PLUS. The
Makefile needed to be tweaked because when building for am33xx, the
SPL will not fit into SRAM if the pruss driver is built into it.
Logic was added to the pruss
The pruicssclkctrl register needs to be added to the cm_perpll register
structure in order to allow the pruss driver to enable the clock for it
during the pruss probe function call on am33xx
This patch depends on patch 0002 of this patch series.
Signed-off-by: Greg Leonberg
---
This series adds support for the pruss/pru_rproc drivers on am33xx and
am57xx SoCs.
All PRU interfaces pru0 and pru1 are supported on am33xx.
All PRU interfaces pru0, pru1, pru2, and pru3 are supported on am57xx.
Testing is done via the "rproc" U-Boot command.
This patch series is based on
The pruss1_clkctrl and pruss2_clkctrl registers need to be added to the
prcm register structure in order to allow the pruss driver to enable the
clock for each of them during the pruss probe function calls for am57xx
Signed-off-by: Greg Leonberg
---
arch/arm/include/asm/omap_common.h| 2
On Wed, Jul 27, 2022 at 09:01:15PM +0200, Pali Rohár wrote:
> On Wednesday 27 July 2022 14:58:20 Tom Rini wrote:
> > On Wed, Jul 27, 2022 at 08:52:01PM +0200, Pali Rohár wrote:
> > > On Wednesday 27 July 2022 14:48:23 Tom Rini wrote:
> > > > On Wed, Jul 27, 2022 at 08:34:41PM +0200, Pali Rohár
On Wednesday 27 July 2022 14:58:20 Tom Rini wrote:
> On Wed, Jul 27, 2022 at 08:52:01PM +0200, Pali Rohár wrote:
> > On Wednesday 27 July 2022 14:48:23 Tom Rini wrote:
> > > On Wed, Jul 27, 2022 at 08:34:41PM +0200, Pali Rohár wrote:
> > > > On Monday 25 July 2022 17:21:00 Tom Rini wrote:
> > > >
On Wed, Jul 27, 2022 at 08:52:01PM +0200, Pali Rohár wrote:
> On Wednesday 27 July 2022 14:48:23 Tom Rini wrote:
> > On Wed, Jul 27, 2022 at 08:34:41PM +0200, Pali Rohár wrote:
> > > On Monday 25 July 2022 17:21:00 Tom Rini wrote:
> > > > On Sun, Jul 10, 2022 at 01:42:56PM +0200, Pali Rohár wrote:
On Wednesday 27 July 2022 14:48:23 Tom Rini wrote:
> On Wed, Jul 27, 2022 at 08:34:41PM +0200, Pali Rohár wrote:
> > On Monday 25 July 2022 17:21:00 Tom Rini wrote:
> > > On Sun, Jul 10, 2022 at 01:42:56PM +0200, Pali Rohár wrote:
> > >
> > > > CONFIG_PREBOOT just cause putting
On Wed, Jul 27, 2022 at 08:34:41PM +0200, Pali Rohár wrote:
> On Monday 25 July 2022 17:21:00 Tom Rini wrote:
> > On Sun, Jul 10, 2022 at 01:42:56PM +0200, Pali Rohár wrote:
> >
> > > CONFIG_PREBOOT just cause putting "preboot=CONFIG_PREBOOT" into env list.
> > > Value CONFIG_PREBOOT="run
Hi
Il mer 27 lug 2022, 20:43 Pali Rohár ha scritto:
> On Wednesday 27 July 2022 20:41:51 Michael Nazzareno Trimarchi wrote:
> > Hi
> >
> > Il mer 27 lug 2022, 20:40 Pali Rohár ha scritto:
> >
> > > On Wednesday 27 July 2022 14:55:51 Michael Nazzareno Trimarchi wrote:
> > > > Hi Pali
> > > >
>
On Wednesday 27 July 2022 20:41:51 Michael Nazzareno Trimarchi wrote:
> Hi
>
> Il mer 27 lug 2022, 20:40 Pali Rohár ha scritto:
>
> > On Wednesday 27 July 2022 14:55:51 Michael Nazzareno Trimarchi wrote:
> > > Hi Pali
> > >
> > > On Wed, Jul 27, 2022 at 2:49 PM Pali Rohár wrote:
> > > >
> > >
Hi
Il mer 27 lug 2022, 20:40 Pali Rohár ha scritto:
> On Wednesday 27 July 2022 14:55:51 Michael Nazzareno Trimarchi wrote:
> > Hi Pali
> >
> > On Wed, Jul 27, 2022 at 2:49 PM Pali Rohár wrote:
> > >
> > > Linux kernel uses compatible string
> "marvell,armada370-nand-controller" for
> > > nand
On Wednesday 27 July 2022 14:55:51 Michael Nazzareno Trimarchi wrote:
> Hi Pali
>
> On Wed, Jul 27, 2022 at 2:49 PM Pali Rohár wrote:
> >
> > Linux kernel uses compatible string "marvell,armada370-nand-controller" for
> > nand controllers on Armada 370/XP/38x. U-Boot currently uses mix of
> >
On Monday 25 July 2022 17:21:00 Tom Rini wrote:
> On Sun, Jul 10, 2022 at 01:42:56PM +0200, Pali Rohár wrote:
>
> > CONFIG_PREBOOT just cause putting "preboot=CONFIG_PREBOOT" into env list.
> > Value CONFIG_PREBOOT="run preboot" in defconfig is just nonsense and does
> > not do anything useful
Edge Compute Module 0 Carrier is an industrial form factor evaluation
board from Edgeble AI.
General features:
- microSD slot
- 2x MIPI CSI2 connectors
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RV1126 SoC.
Both eMMC and SD boot are tested in Edge Compute Module 0.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rv1126-u-boot.dtsi | 62 +
1 file changed, 62 insertions(+)
create mode
Edge Compute Module 0 Carrier is an industrial form factor evaluation
board from Edgeble AI.
General features:
- microSD slot
- 2x MIPI CSI2 connectors
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC
Edge Compute Module 0 is a 96boards SoM-CB compute module based
on Rockchip RV1126 from Edgeble AI.
General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 16GB eMMC
- Fn-link 8223A-SR WiFi/BT
Edge Compute Module 0 needs to mount on top of Edgeble AI Carrier
boards for creating complete platform
Add support for rv1126 package header in mkimage tool.
Signed-off-by: Jagan Teki
---
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 1325aa83cb..f18b6fad95 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -133,6 +133,7 @@
Add common rv1126 include config.
Signed-off-by: Jagan Teki
---
include/configs/rv1126_common.h | 42 +
1 file changed, 42 insertions(+)
create mode 100644 include/configs/rv1126_common.h
diff --git a/include/configs/rv1126_common.h
Unsecure the dram area so that MMC, USB, and SFC controllers
can able to read data from dram.
Signed-off-by: Jason Zhu
Signed-off-by: Jagan Teki
---
arch/arm/mach-rockchip/rv1126/rv1126.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c
Rockchip RV1126 is a high-performance vision processor SoC
for IPC/CVR, especially for AI related application.
Add arch core support for it.
Signed-off-by: Jagan Teki
---
arch/arm/include/asm/arch-rv1126/boot0.h | 11
arch/arm/include/asm/arch-rv1126/gpio.h | 11
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports
Add pinctrl definitions for Rockchip RV1126.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rv1126-pinctrl.dtsi | 302 +++
1 file changed, 302 insertions(+)
create mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi
diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi
Add GRF header for Rockchip RV1126.
Signed-off-by: Jagan Teki
---
.../include/asm/arch-rockchip/grf_rv1126.h| 251 ++
1 file changed, 251 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rv1126.h
diff --git
Add the dt-bindings header for the Rockchip RV1126, that gets shared
between the clock controller and the clock references in the dts.
Signed-off-by: Finley Xiao
Signed-off-by: Jagan Teki
---
include/dt-bindings/clock/rv1126-cru.h | 632 +
1 file changed, 632
Add clock driver support for Rockchip RV1126 SoC.
Signed-off-by: Joseph Chen
Signed-off-by: Jagan Teki
---
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk_rv1126.c | 1889 +
2 files changed, 1890 insertions(+)
create mode 100644
Add power-domain header for RV1126 SoC from description in TRM.
Signed-off-by: Elaine Zhang
Signed-off-by: Jagan Teki
---
include/dt-bindings/power/rv1126-power.h | 35
1 file changed, 35 insertions(+)
create mode 100644 include/dt-bindings/power/rv1126-power.h
diff
Add clock and reset unit header include for rv1126.
Signed-off-by: Jagan Teki
---
.../include/asm/arch-rockchip/cru_rv1126.h| 459 ++
1 file changed, 459 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rv1126.h
diff --git
Add pinctrl driver for Rockchip RV1126.
Signed-off-by: Jianqun Xu
Signed-off-by: Jagan Teki
---
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rv1126.c | 416 ++
2 files changed, 417 insertions(+)
create mode 100644
Some pins in rockchip are routed via Top GRF and PMU GRF
instead of direct regmap.
Add support to handle all these routing paths so that the
SoC pinctrl drivers will use them accordingly.
Signed-off-by: Jianqun Xu
Signed-off-by: Jagan Teki
---
drivers/pinctrl/rockchip/pinctrl-px30.c |
Add DDR driver for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
.../asm/arch-rockchip/dram_spec_timing.h | 452 +++
.../include/asm/arch-rockchip/sdram_common.h | 212 +
.../include/asm/arch-rockchip/sdram_msch.h| 12 +
Add LPDDR4 detection timings and support for RV1126.
Signed-off-by: Jagan Teki
---
.../sdram-rv1126-lpddr4-detect-1056.inc | 78 +++
.../sdram-rv1126-lpddr4-detect-328.inc| 78 +++
.../sdram-rv1126-lpddr4-detect-396.inc| 78
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG
instead of printing by default.
This gives an option to configs to enable these prints or
not.
Signed-off-by: Jagan Teki
---
drivers/ram/rockchip/sdram_rv1126.c | 38 +++--
1 file changed, 25 insertions(+), 13
Add DDR loader parameters for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
.../rockchip/sdram-rv1126-loader_params.inc | 198 ++
1 file changed, 198 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rv1126-loader_params.inc
diff
Add DDR3 detection timings for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
.../sdram-rv1126-ddr3-detect-1056.inc | 72 +++
.../rockchip/sdram-rv1126-ddr3-detect-328.inc | 72 +++
High row detection for non-8bit bw requires axi split.
So, update the existing high row detection code in order
to support full bw chips.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
.../include/asm/arch-rockchip/sdram_common.h | 2 +-
drivers/ram/rockchip/sdram_common.c
Add full ddr pctl registers and bit masks for px30.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
.../asm/arch-rockchip/sdram_pctl_px30.h | 100 +-
drivers/ram/rockchip/sdram_pctl_px30.c| 6 +-
2 files changed, 101 insertions(+), 5 deletions(-)
diff
DDR chip capacity is computed based on GRF split in some
Rockchip SoC's like PX30 and RV1126.
Add split argument in ddr print info so-that the respective
ddr driver will pass the grf split.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
Rockchip PX30 has 16KB sram, bootrom reserved 4KB as stack.
Correct it.
Signed-off-by: Jagan Teki
---
tools/rkcommon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 0db45c2d41..1325aa83cb 100644
--- a/tools/rkcommon.c
+++
We have common ddr types in rockchip or in general. So use
the common ddr type names instead of per Rockchip SoC to
avoid confusion.
The respective ddr type names will use on the associated
ddr SoC driver as these drivers are built per SoC at a time.
Signed-off-by: Jagan Teki
---
ram-uclass is building irrespective of whether TPL_DM
or SPL_DM is enabled. So control the ram uclass build
based on TPL/SPL_DM.
Signed-off-by: Jagan Teki
---
drivers/ram/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
From: Jagan Teki
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
This patch series add basic core support for Rockchip RV1126
and boot from eMMC and SD.
Linux support is under review for the same [2].
Tested RV1126 in Edgeble AI Edge
Introduce BSH SystemMaster (SMM) M2 board family, which consists of:
imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards.
Add support for imx6ulz BSH SMM M2 board:
- 128 MiB DDR3 RAM
- 256MiB Nand
- USBOTG1 peripheral - fastboot.
Signed-off-by: Michael Trimarchi
---
Changes V2->V3:
- remove
> Add binding header for i.MXRT1170 pinctrl device tree.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang
> Add the clock binding doc for i.MXRT1170.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235
> The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
> evaluation of the i.MXRT, which features NXP's implementation of the Arm
> Cortex-M7 and Cortex-M4 core.
> The EVK provides 64 MB SDRAM, Micro SD card socket,
> USB 2.0 OTG.
> This patch aims to support the preliminary
> Add clock driver support for i.MXRT1170.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235
> The i.MXRT11 series has two new pll types but are variants of existing.
> This patch adds the ability to read one of the pll types' frequency
> as it can't be changed unlike the generic pll it also has the
> division factors swapped.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master,
> Add a base defconfig for the i.MXRT1170
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235
> This commit adds board support for i.MXRT1170-EVK from NXP. This board
> is an evaluation kit provided by NXP for i.MXRT117x processor family.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> The i.MXRT11 series has different offsets for IOCR_MUX, it also can
> address 64MiB of SDRAM so add a macro for that.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX
pulled from kernel tag v5.18
---
scripts/config | 230 +
1 file changed, 230 insertions(+)
create mode 100755 scripts/config
diff --git a/scripts/config b/scripts/config
new file mode 100755
index 00..ff88e2faef
--- /dev/null
+++
Hi Stefano
On Wed, Jul 27, 2022 at 5:02 PM Stefano Babic wrote:
>
> On 17.07.22 17:56, Michael Trimarchi wrote:
> > Introduce BSH SystemMaster (SMM) M2 board family, which consists of:
> > imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards.
> >
> > Add support for imx6ulz BSH SMM M2 board:
> >
> > -
> Date: Wed, 27 Jul 2022 17:59:02 +0200
> From: Michal Simek
>
> On 7/27/22 16:34, Mark Kettenis wrote:
> > The contents of differ between OSes. It may only define
> > the relocation types for the host architecture, and may not contain
> > machine-specific defines for more obscure
Hi Simon,
On Tue, Jul 26, 2022 at 01:53:44PM -0600, Simon Glass wrote:
> On Tue, 26 Jul 2022 at 10:25, John Keeping wrote:
> >
> > Upstream device trees now use standard node names like "gpio@ff..." but
> > the rk_gpio driver expects a name like "gpio0@ff..." (note the index
> > before the @).
>
On 7/27/22 17:07, Martin Bonner wrote:
Martin
On Wed, 27 Jul 2022 at 14:29, Heinrich Schuchardt mailto:xypron.g...@gmx.de>> wrote:
On 7/25/22 09:42, Martin Bonner wrote:
> * Add three more modules that are required.
> * Remove the version numbers (because they are hard to keep
On 7/27/22 16:34, Mark Kettenis wrote:
The contents of differ between OSes. It may only define
the relocation types for the host architecture, and may not contain
machine-specific defines for more obscure architectures (such as
Microblaze) at all.
Define the relevant constants for
In file included from include/linux/bitops.h:22,
from include/log.h:15,
from include/linux/printk.h:4,
from include/common.h:20,
from lib/lz4_wrapper.c:6:
lib/lz4_wrapper.c: In function ‘ulz4fn’:
include/linux/kernel.h:184:17:
On Wed, Jul 27, 2022 at 04:15:52PM +0100, Martin Bonner wrote:
> Martin
>
>
> On Wed, 27 Jul 2022 at 15:15, Tom Rini wrote:
>
> > On Wed, Jul 27, 2022 at 03:56:07PM +0200, Heinrich Schuchardt wrote:
> > > On 7/27/22 15:51, Heinrich Schuchardt wrote:
> > > > On 7/27/22 15:29, Heinrich
U-Boot for initial L2 SRAM uses L2 memory-mapping mode and not L2 with
locked lines. P2020 reference manual about L2 memory-mapping mode says:
Accesses to memory-mapped SRAM are cacheable only in the corresponding
e500 L1 caches.
So there is no need to set Caching-Inhibit I-bit for second
Martin
On Wed, 27 Jul 2022 at 15:15, Tom Rini wrote:
> On Wed, Jul 27, 2022 at 03:56:07PM +0200, Heinrich Schuchardt wrote:
> > On 7/27/22 15:51, Heinrich Schuchardt wrote:
> > > On 7/27/22 15:29, Heinrich Schuchardt wrote:
> > > > On 7/25/22 09:42, Martin Bonner wrote:
> > > > > * Add three
As per https://github.com/actions/virtual-environments/issues/5583 the
macOS-10.15 image is being deprecated. Move us up to macOS-12.
Signed-off-by: Tom Rini
---
.azure-pipelines.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
Martin
On Wed, 27 Jul 2022 at 14:29, Heinrich Schuchardt
wrote:
> On 7/25/22 09:42, Martin Bonner wrote:
> > * Add three more modules that are required.
> > * Remove the version numbers (because they are hard to keep in sync
> >with the latest MSYS2 versions)
> > * Add a pacman command
On 17.07.22 17:56, Michael Trimarchi wrote:
Introduce BSH SystemMaster (SMM) M2 board family, which consists of:
imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards.
Add support for imx6ulz BSH SMM M2 board:
- 128 MiB DDR3 RAM
- 256MiB Nand
- USBOTG1 peripheral - fastboot.
The contents of differ between OSes. It may only define
the relocation types for the host architecture, and may not contain
machine-specific defines for more obscure architectures (such as
Microblaze) at all.
Define the relevant constants for Microblaze locally if they are
not provided by .
On 7/27/22 15:35, Enric Balletbo i Serra wrote:
This implements the following command:
part type mmc 0:1
-> print partittion type UUID
%s/partittion/partition/
part type mmc 0:1 uuid
-> set environment variable to partition type UUID
"part type" can be useful when
On Wed, Jul 27, 2022 at 03:56:07PM +0200, Heinrich Schuchardt wrote:
> On 7/27/22 15:51, Heinrich Schuchardt wrote:
> > On 7/27/22 15:29, Heinrich Schuchardt wrote:
> > > On 7/25/22 09:42, Martin Bonner wrote:
> > > > * Add three more modules that are required.
> > > > * Remove the version numbers
On Wed, Jul 27, 2022 at 03:35:34PM +0200, Enric Balletbo i Serra wrote:
> This implements the following command:
>
> part type mmc 0:1
> -> print partittion type UUID
> part type mmc 0:1 uuid
> -> set environment variable to partition type UUID
>
> "part type" can be useful
On 7/25/22 09:45, Martin Bonner wrote:
Describe exactly which bytes are hashed and in what order
when signing a configuration.
Signed-off-by: Martin Bonner
This is not a valid patch. Please, use git send-email to send patches.
$ git am /tmp/1.patch
Applying: Provide more details of exactly
On 7/27/22 15:51, Heinrich Schuchardt wrote:
On 7/27/22 15:29, Heinrich Schuchardt wrote:
On 7/25/22 09:42, Martin Bonner wrote:
* Add three more modules that are required.
* Remove the version numbers (because they are hard to keep in sync
with the latest MSYS2 versions)
* Add a pacman
On 7/27/22 15:29, Heinrich Schuchardt wrote:
On 7/25/22 09:42, Martin Bonner wrote:
* Add three more modules that are required.
* Remove the version numbers (because they are hard to keep in sync
with the latest MSYS2 versions)
* Add a pacman command line to install everything.
This implements the following command:
part type mmc 0:1
-> print partittion type UUID
part type mmc 0:1 uuid
-> set environment variable to partition type UUID
"part type" can be useful when writing a bootcmd which searches for a
specific partition type to enable automatic
On 7/25/22 09:42, Martin Bonner wrote:
* Add three more modules that are required.
* Remove the version numbers (because they are hard to keep in sync
with the latest MSYS2 versions)
* Add a pacman command line to install everything.
Signed-off-by: Martin Bonner
Your mail is not a valid
On Mon, Jul 25, 2022 at 05:06:15PM +0200, Marek Behún wrote:
> After a discussion with Tom Rini, we've agreed that I am going to take
> over custodianship of the MPC85XX platform, since it seems other people
> do not have necessary interest or time and getting things done over
> there takes too
On Tue, Jul 26, 2022 at 10:27:01AM +0200, Alexander Dahl wrote:
> Hei hei,
>
> once again I tried building U-Boot with CONFIG_TOOLS_LIBCRYPTO disabled and
> with no libssl-dev installed on the build machine. It does not work.
>
> Even porting the patch disabling the build with kwbimage (see
On Wed, Jul 27, 2022 at 05:01:03PM +0900, Jaehoon Chung wrote:
> Dear Tom,
>
> Please pull u-boot-mmc master into u-boot master branch.
> If there is any problem, let me know, plz.
>
> Best Regards,
> Jaehoon Chung
>
> CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/12906
>
On Wed, Jul 27, 2022 at 03:25:16PM +0900, Jaehoon Chung wrote:
> Dear Tom,
>
> Please pull u-boot-pmic master into u-boot master branch.
> If there is a problem, let me know, plz
>
> Best Regards,
> Jaehoon Chung
>
> CI: https://source.denx.de/u-boot/custodians/u-boot-pmic/-/pipelines/12905
>
On Tue, Jul 26, 2022 at 10:37:03PM -0600, Simon Glass wrote:
> Hi Tom,
>
> Build here:
>
> https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/12903
>
>
> The following changes since commit 6e15cda270a060cf87c6c643a1cc3da65ffb242d:
>
> Prepare v2022.10-rc1 (2022-07-25 20:31:12
There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin,
which is routed to CN11 pin header, is documented as SPI CS1, but
MPP[26] pin does not support this function. Instead it controls chip
select 2 if in "spi0" mode.
Fix the name of the pin node in pinctrl node and fix the
Hi Pali
On Wed, Jul 27, 2022 at 2:49 PM Pali Rohár wrote:
>
> Linux kernel uses compatible string "marvell,armada370-nand-controller" for
> nand controllers on Armada 370/XP/38x. U-Boot currently uses mix of
> "marvell,armada370-nand" and "marvell,mvebu-pxa3xx-nand".
>
> So unify it and use just
* Add SPDX-License-Identifier
* Add SFP and LED nodes
* Fix PHY nad NOR nodes
* Remove duplicates from u-boot.dtsi file
Signed-off-by: Pali Rohár
---
.../dts/armada-385-turris-omnia-u-boot.dtsi | 5 +-
arch/arm/dts/armada-385-turris-omnia.dts | 228 ++
2 files changed,
* Replace skeleton.dtsi by explicit #address-cells / #size-cells
* Add sdramc@1400 and phy@18300 nodes
* Remove (unused) timeout-ms i2c properties
* Fix compatible string for UARTs
* Add interrupts properties for watchdog
Signed-off-by: Pali Rohár
---
arch/arm/dts/armada-38x.dtsi | 55
* Define PCIe interrupts
Signed-off-by: Pali Rohár
---
arch/arm/dts/armada-385.dtsi | 52 ++--
1 file changed, 44 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/armada-385.dtsi b/arch/arm/dts/armada-385.dtsi
index 581a7d9beac3..48072fc7fd4a 100644
---
Linux kernel uses compatible string "marvell,armada370-nand-controller" for
nand controllers on Armada 370/XP/38x. U-Boot currently uses mix of
"marvell,armada370-nand" and "marvell,mvebu-pxa3xx-nand".
So unify it and use just Linux kernel compatible string.
Signed-off-by: Pali Rohár
---
> -Original Message-
> From: Tim Harvey
> Sent: 2022年7月23日 10:23
> To: Bough Chen
> Cc: Peng Fan ; Jaehoon Chung
> ; Fabio Estevam ; Sean
> Anderson ; u-boot ; Marek
> Vasut ; Adam Ford ; Andrey Zhizhikin
> ; dl-uboot-imx
> Subject: Re: [PATCH 3/3] mmc: fsl_esdhc_imx: correct the
[Adding Josua]
On Tue, Jul 26, 2022 at 3:12 PM Tom Rini wrote:
> So, funny issue here now. With:
> commit d0399a46e7cda63c07e3eb8558bef84cfb068028
> Author: Marcel Ziswiler
> Date: Thu Jul 21 15:27:26 2022 +0200
>
> imx6dl/imx6qdl: synchronise device trees with linux
>
> Synchronise
hi Ilias,
On Wed, 20 Jul 2022 at 13:06, Ilias Apalodimas
wrote:
>
> Hi Sughosh,
>
> >
> > > + nimages = CONFIG_FWU_NUM_IMAGES_PER_BANK;
> > > + active_bank = mdata->active_index;
> > > + img_entry = >img_entry[0];
> > > + for (i = 0; i < nimages; i++) {
> > > +
On Tue, Jul 12, 2022 at 12:00:23PM +0100, Andre Przywara wrote:
> The generic ARM relocate_code function was using its own function entry
> point as a relocation base, and it was obtaining that address by using
> the "adr" instruction on that entry point label.
> However that label is not just an
Hi Simon,
On 7/26/22 21:58, Simon Glass wrote:
Hi Quentin,
On Tue, 26 Jul 2022 at 03:08, Quentin Schulz
wrote:
Hi Xavier,
On 7/25/22 19:33, Xavier Drudis Ferran wrote:
El Mon, Jul 25, 2022 at 07:29:53PM +0200, Xavier Drudis Ferran deia:
I copy here the rockchip-u-boot.dtsi file and then
Currently for all Qcom SoCs/boards there are separate compatibles for
GPIO and pinctrl. But this is inconsistent with official (upstream) Linux
bindings which requires only a single compatible "qcom,-pinctrl"
and there is no such compatible property as "qcom,tlmm-".
So fix this inconsistency for
DT compatible is sufficient to make platform specific differentiation,
so remove redundant CONFIG_SDM845 check.
Signed-off-by: Sumit Garg
---
arch/arm/mach-snapdragon/Makefile | 2 +-
arch/arm/mach-snapdragon/pinctrl-snapdragon.c | 2 --
2 files changed, 1 insertion(+), 3
This is an initial step towards achieving complete Linux DT sync on Qcom
SoCs/boards. It syncs up DT compatibles for pinctrl and GPIO drivers.
Changes in v2:
- Separate patch for CONFIG_SDM845 check removal.
- Fix pinctrl DT compatibles for db410c and db820c.
Sumit Garg (2):
pinctrl: sdm845:
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