No comment on the commit itself, but does it really need all of the
marketing BS at the top?
On May 30, 2014 3:22 AM, "Alison Wang" wrote:
> This series contain the support for Freescale LS102xA SoC and LS1021AQDS
> board.
>
> The QorIQ LS1 family is built on Layerscape architecture, the industry
On Fri, Apr 12, 2013 at 7:10 AM, TENART Antoine wrote:
> Signed-off-by: Antoine Tenart
> ---
> MAINTAINERS|4 +
> arch/arm/include/asm/arch-am33xx/spl.h |9 +
> board/ti/ti816x/Makefile | 48 ++
> board/ti/ti816x/evm.c | 866
On Fri, Apr 12, 2013 at 7:10 AM, TENART Antoine wrote:
> Signed-off-by: Antoine Tenart
> ---
> arch/arm/include/asm/arch-am33xx/clock.h |4 +
> arch/arm/include/asm/arch-am33xx/clocks_ti816x.h | 136
> arch/arm/include/asm/arch-am33xx/cpu.h |4 +
> arch
On Tue, Jan 29, 2013 at 11:13 AM, Gabor Juhos wrote:
> 2013.01.29. 11:44 keltezéssel, Daniel Schwierzeck írta:
> > 2013/1/29 Gabor Juhos :
> >> The patch adds an unified linker script file which
> >> can be used for all currently supported MIPS targets.
> >>
> >> Signed-off-by: Gabor Juhos
> >>
On Wed, Jan 23, 2013 at 6:58 AM, Michal Simek wrote:
> From: Jagannadha Sutradharudu Teki <
> jagannadha.sutradharudu-t...@xilinx.com>
>
> Add support for Numonyx N25Q064 SPI flash.
>
> Signed-off-by: Jagannadha Sutradharudu Teki
> Signed-off-by: Michal Simek
> ---
> drivers/mtd/spi/stmicro.c |
On Thu, Jan 17, 2013 at 5:19 AM, David Aldrich
wrote:
> Hi
>
> I am using an Advantech TMX320TCI6614 EVM to develop code for an ARM core
> on a TI C66x device. The ARM core runs:
>
> U-Boot 2011.06-2-gc4611c1-dirty (May 30 2012 - 15:38:01)
>
> I have booted this target card for several months
Same issue here with OUTPUT_FORMAT as the other linker script.
On Aug 17, 2012 10:33 AM, "Zhizhou Zhang" wrote:
> Signed-off-by: Zhizhou Zhang
> ---
> board/qemu-mips/u-boot.lds |8
> 1 file changed, 8 insertions(+)
>
> diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-bo
I think the OUTPUT_FORMAT line if wrong. This will produce little endian
output even if explicitly told by command line switch -EB to make big
endian.
On Aug 17, 2012 10:33 AM, "Zhizhou Zhang" wrote:
> Signed-off-by: Zhizhou Zhang
> ---
> examples/standalone/mips64.lds | 59
> +++
, Aug 16, 2012 at 8:29 PM, Andrew Dyer wrote:
> > I don't have any comment on the body of the patch, but calling this an
> i2s
> > patch is misleading. I2s is a generic standard for moving stereo audio
> > around, and many chips support it.
> >
> > This
I don't have any comment on the body of the patch, but calling this an i2s
patch is misleading. I2s is a generic standard for moving stereo audio
around, and many chips support it.
This patch looks like i2s support for a specific codec chip and the
filenames should reflect that.
_
On Fri, Nov 25, 2011 at 02:44, Marek Vasut wrote:
> > This handler can be activated on multi-processor systems to boot only
> > the master CPU. All slave CPUs are halted by executing the WAIT
> > instruction. This is also useful to reduce the power consumption at
> > boot time.
> >
> > Signed-off
On Tue, Jul 5, 2011 at 10:50, Scott Wood wrote:
> On Fri, 1 Jul 2011 23:16:01 -0700
> Ran Shalit wrote:
>
>> > I wanted to write different parts of the page each time. And now I
>> undertsand that
>> the ECC is stored for each page, which mean that what I am trying to do , is
>> impossible (if I
On Sun, Feb 27, 2011 at 10:32, Wolfgang Denk wrote:
> Dear Albert ARIBAUD,
>
> In message <4d67e64a.1090...@free.fr> you wrote:
>>
>> > I have been trying to compile the HexAIS files found in the tarball, but
>> > facing some issues. Will check this problem, to see if a way can be
>> > found to ch
On Mon, Feb 7, 2011 at 16:58, Scott Wood wrote:
> On Mon, Jan 31, 2011 at 06:56:48PM -0800, Aaron Williams wrote:
>> Trying again submitting the patch.
>>
>> /* Do manufacturer-specific fixups */
>> switch (info->manufacturer_id) {
>> + case 0x:
>>
On Tue, Jan 25, 2011 at 19:56, Aaron Williams
wrote:
> I ran into a problem with the Spansion S29GL064N flash chip in that it returns
> a manufacturer ID of 0 and it also requires the AMD geometry fixup.
>
> Additionally, I modified a few print statements to use KiB/MiB instead of
> kB/MB.
>
> -Aa
On Dec 1, 2010 12:26 AM, "奥刘" wrote:
> In the file .\cpu\mips\cache.s , i found some code confounded .
>
> line 152 to line 156 :
>
> cache_op Index_Store_Tag_I t0
> PTR_ADDU t0, a2
> bne t0, t1, 1b
> /* fill
On Wed, Oct 20, 2010 at 21:28, sunimohan wrote:
>
> Hi
>
> I have connected my mini2440 to a Com device using serial port.
>
> when I try to boot, uboot always drops into the shell. If I remove the
> serial port connector, it boots happily.
>
> Looks like the Com device is responding to the boot
On Sun, Sep 12, 2010 at 17:38, Peter Tyser wrote:
> Using -fno-toplevel-reorder causes gcc to not reorder functions. This
> ensures that an application's entry point will be the first function in
> the application's source file.
>
> This change, along with commit 620bbba524fbaa26971a5004793010b16
On Tue, Jul 20, 2010 at 4:37 AM, Wolfgang Denk wrote:
> Dear Xiangfu Liu,
>
> In message <4c453325.4080...@openmobilefree.net> you wrote:
>>
>> which compiler in ELDK if for the mips_el system?
>
> GCC, of course :-)
>
>> I guess there are some different between ELDK cross compiler
>> and OpenWrt
On Sun, Jul 11, 2010 at 5:55 PM, Mike Frysinger wrote:
> On Wednesday, July 07, 2010 00:45:42 Andrew Dyer wrote:
>> On Tue, Jul 6, 2010 at 1:14 AM, Thomas Chou wrote:
>> > We should not set SDA after TRISTATE, as it results in contention.
>> >
>
On Tue, Jul 6, 2010 at 1:14 AM, Thomas Chou wrote:
> We should not set SDA after TRISTATE, as it results in contention.
>
> Signed-off-by: Thomas Chou
> ---
> drivers/i2c/soft_i2c.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2
On Tue, Jun 29, 2010 at 2:28 PM, Todd Fischer wrote:
> Hi,
>
> We are seeing NOR write failures on 6 of the 10 boards (DM6446 ARM SoC
> with Numonyx JS28F256M29EWL NOR flash chip). Four of the boards seem to
> work without error. All 10 boards were made on the same manufacturing
> line at the sa
On Tue, Jun 22, 2010 at 4:29 PM, Wolfgang Denk wrote:
> Dear Jochen Friedrich,
>
> In message <1274031318-22876-1-git-send-email-joc...@scram.de> you wrote:
>> similar to 274737e5eb25b2bcd3af3a96da923effd543284f
>>
>> This patch changes get_timer() for sa1100 to return the time since
>> 'base' ins
Ronetix Development Tools GmbH
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * Version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the ho
On Sun, May 9, 2010 at 10:50 AM, Gurumurthy G M
wrote:
> Hi Andrew,
> Find attached disassembly file and register dump. let me know if you
> find any mistake or am missing something.
>
code looks pretty normal. Check that t9 (aka register 25) is set up
on entry to the function. I beli
On Sat, May 8, 2010 at 11:29 AM, Gurumurthy G M
wrote:
>
> Hi All,
> I am getting a exception in board.c , at the end of serial_init
> function i.e. when i access to stack pointer (SP).
>
> The return address register ra value is not correct.
>
> I am porting U-boot-2010.03 for MIPS32 Au135
On Mon, Apr 26, 2010 at 2:07 PM, Gurumurthy G M
wrote:
>
>
> Hi Andrew,
> Thank You very much for the reply.
>
> i have done a couple of porting for MPC82xx,MPC74xx i.e. only worked on Free
> Scale processors. this is my first port on MIPS. i feel its not so simple as
> MPC and ARM.
>
>
2010/4/23 Gurumurthy G M :
>
>
> let me know if anyone have ported u-boot to MIPS32.
I did a couple of ports for Au1550 boards back when it was still owned by AMD.
On Au1550 if the boot pins are set up for NOR flash, the CS0 line is
mapped with a base physical address 0x0_1fc0_ (36 bit physic
On Wed, Mar 24, 2010 at 4:10 PM, Wolfgang Denk wrote:
> Dear Mike,
>
> In message
> you
> wrote:
>>
>> What is the purpose of CONFIG_PCI_BOOTDELAY? I am using uboot version
>
> Adding a delay so the PCI controllers can come up and stabilize.
>
>> Specifically in my case, all the resets on my bo
On Sat, Feb 27, 2010 at 5:40 AM, Balaji Sivakumar, ERS, HCLTech
wrote:
> Hi,
> We have developed new board with TMS320DM6467, My question here is can I use
> same the U-boot.bin that came with DM6467 EVM.
> We are using the RBL supported Nand Device and no change in the memory map.
> The only I
On Sun, Jan 31, 2010 at 10:10 AM, Chetan Nanda wrote:
> Hi Wolfgang,
>
> On Sun, Jan 31, 2010 at 9:27 PM, Wolfgang Denk wrote:
>
>> Dear Chetan Nanda,
>>
>> In message <7f245da81001310745i8e54f9dr95cb4c0af0a74...@mail.gmail.com>
>> you wrote:
>> >
> Of course chances are that your USB serial ada
On Mon, Oct 26, 2009 at 1:41 AM, XR SU wrote:
> hi,all:
> here is a question, who can tell me? thanks.
>
> in uboot file : cpu/mips/start.S
>
> /* Initialize GOT pointer. */
> bal 1f
> nop
> .word _GLOBAL_OFFSET_TABLE_
> 1:
> move gp, ra
> l
On Mon, Oct 12, 2009 at 10:10 AM, wrote:
> Thanks for 1) and 2).
> For 3), both results show GP register is modified.
> the result of ${CROSS_COMPILE}objdump --source cpu.o is:
>
> void flush_cache(ulong start_addr, ulong size)
> {
> 7c: 3c1c lui gp,0x0
> 80: 279c
On Mon, Oct 12, 2009 at 5:11 PM, Andrew Dyer wrote:
> On Mon, Oct 12, 2009 at 10:10 AM, wrote:
>> Thanks for 1) and 2).
>> For 3), both results show GP register is modified.
>> the result of ${CROSS_COMPILE}objdump --source cpu.o is:
>>
>> void flush_c
On Sat, Oct 10, 2009 at 12:27 PM, wrote:
> On Fri, 09 Oct 2009 12:16 -0500, "Andrew Dyer" wrote:
>> On Fri, Oct 9, 2009 at 11:21 AM, wrote:
>> > I think I found a problem in cpu/mips/start.S.
>> >
>> > gp register is used to point to the SDRAM. Bu
On Mon, Oct 5, 2009 at 8:23 AM, Simon Kagstrom
wrote:
> U-boot for Marvell Kirkwood boards no longer work after the EABI changes
> introduced in commit f772acf8a584067033eff1e231fcd1fb3a00d3d9. This
> turns out to be caused by a stack alignment issue. The armv5te
> instructions ldrd/strd instructi
On Thu, Sep 3, 2009 at 11:09 AM, Becky Bruce wrote:
> This makes sense to me. The disable function would need to flush the
> range from the cache, but that's the only difficulty I forsee.
> However, I dug up some AVR32 docs, and it looks like the whole dual
> cacheable/CI mapping thing may be arch
On Tue, Sep 1, 2009 at 12:50 PM, Brian Hutchinson wrote:
> Hi all,
>
> I'm a little stumped as to how to write to a EEPot with the imw command.
>
> The EEPot is a Maxim 5434 and has an address of 0x28. To write to its
> volatile or non-volatile register ... a command byte is given.
>
> Writing 5 b
On Mon, Aug 17, 2009 at 4:48 PM, Wolfgang Denk wrote:
> Dear uday bhaskar,
>
> please keep the mailing list on cc:
>
> In message <75bad7120908170826l6c4f494q480208f55ac93...@mail.gmail.com> you
> wrote:
>>
>> Actually i have ARM7 based LPC2129 board taken from Emblitz
>> (www.emblitz.com).
>> Bo
On Mon, Aug 17, 2009 at 12:58 PM, Jake Peavy wrote:
> Hi all,
>
> As I feel this list is a good resource for embedded design minds, please
> forgive this elementary question.
>
> As NOR flash ages, does write speed degrade? Or do writes take place at
> roughly the same rate over time until the par
We noticed in the TI distribution of u-boot (1.2.0) that if you point
the u-boot ns16550.c serial driver at a UART other than uart0, it
doesn't work. We believe the issue also exists in the current
version.
The root problem is that the MDR1 register in the UART defaults to
disabled. We believe t
On Wed, Jun 24, 2009 at 3:09 AM, Prafulla Wadaskar wrote:
>> I don't see anything in the 88E6161 switch itself that would
>> respond at those 0xEE addresses (IIRC the MII bus only
>> provides for 5 bits of register and phy address). Is this
>> something specific to the board/SoC you were running t
Hi, I am in the midst of bringing up a board using the 88E6161 chip
and was looking at your u-boot driver as an example of how to set it
up (still writing simple tests loaded via JTAG, not the full u-boot).
Our board uses the indirect method of writing to the MII bus
registers, and I think there m
On Wed, Apr 8, 2009 at 1:30 PM, Prafulla Wadaskar wrote:
> Chips supprted:-
> 1. 88E6161 6 port gbe swtich with 5 integrated PHYs
> 2. 88E6165 6 port gbe swtich with 5 integrated PHYs
> Note: This driver is supported and tested against
> kirkwood egiga interface, other interfaces can be added
We
work either way, I have a smart battery(*) that
requires repeated start, and someone at some point found a device that
required a stop-start.
(*)
http://www.inspired-energy.com/Standard_Products/NL2054/NL2054%20Rev1.0%20Data%20Sheet.pdf
Signed-off-by: Andrew Dyer
---
README |9
On Mon, Dec 15, 2008 at 8:51 AM, Stefan Roese wrote:
> This patch adds support for the Micronas VCT board series.
> Currently the following platforms are supported:
>
> vct_premium
> vct_premium_small
> vct_premium_onenand
> vct_premium_onenand_small
> vct_platinum
> vct_platinum_small
> vc
>> I would love to see memory addresses get parsed through a common
>> routine - that would allow easily hooking in an arch/platform specific
>> routine to filter out addresses that should be avoided.
>
> U-Boot is not supposed to do any such filtering.
>
> "UNIX was not designed to stop you from d
On Wed, Nov 26, 2008 at 4:11 PM, Becky Bruce <[EMAIL PROTECTED]> wrote:
> Folks,
>
> We're going to be seeing more platforms with larger physical addresses
> (PA) than virtual addresses (VA) supported in u-boot, and this kind of
> ruins the current assumption inherent in much of u-boot that VA ==
>
On Fri, Oct 10, 2008 at 6:55 AM, Haavard Skinnemoen
<[EMAIL PROTECTED]> wrote:
> "Graeme Russ" <[EMAIL PROTECTED]> wrote:
>> - Am I looking at the problem the wrong way?
>
> No, I think you're on the right track.
>
>> - Has anyone here looked into making U-Boot 100% relocatable before?
>
> I've l
On Mon, Oct 6, 2008 at 7:13 AM, sahar mustafa <[EMAIL PROTECTED]> wrote:
> can you tell me how to change the load address without crippling the u-boot?
It's not 100% clear what you are trying to do, and you didn't mention
your target other than it's MIPS...
If you want to build a version of u-boo
On Thu, Sep 25, 2008 at 3:04 AM, Roman Mashak <[EMAIL PROTECTED]> wrote:
> Hello
>
> Reading u-boot's README paper and trying to figure out a few aspects:
>
> (1) as I know the bootloader sets up memory area for argument passing,
> initializes it with data structures and fill up with the values. Is
On Thu, Sep 25, 2008 at 3:16 AM, Bartlomiej Sieka <[EMAIL PROTECTED]> wrote:
>>> More detailed description can be found in doc/README.au_tftp
'au' as a prefix seems awfully terse and cryptic to me (not to mention
reminding me of Australians and gold), something a bit longer would go
a long way to
> Also, please enlighten me: what is "EFI", and what is a "GUID"
> partition table, and which systems do use that?
EFI is the PC BIOS replacement that Intel came up with, most notably
used on Apple's Intel based computers. A blurb about EFI is here -
http://en.wikipedia.org/wiki/Extensible_Firmwa
On Mon, Sep 22, 2008 at 3:11 PM, Wolfgang Denk <[EMAIL PROTECTED]> wrote:
> Dear Stefan, Kim, Andy, Jon & Kumar,
>
> in message <[EMAIL PROTECTED]>
> Nobuhiro Iwamatsu wrote:
>>
>> I did a simple check.
>>
>> Only powerpc and i386 and sh seem to use PCI.
>> If powerpc does not have a problem, would
On Mon, Sep 8, 2008 at 1:43 PM, Wolfgang Denk <[EMAIL PROTECTED]> wrote:
> Dear Andrew Dyer,
>
> In message <[EMAIL PROTECTED]> you wrote:
>> Add 'reboot' as a synonym for 'reset' at the u-boot command line.
>
> I tend to reject this change, be
Add 'reboot' as a synonym for 'reset' at the u-boot command line.
This saves me confusion when switching back and forth between linux
and u-boot about which command to use by making u-boot accept both.
Signed-off-by: Andrew Dyer <[EMAIL PROTECTED]>
---
common/cmd_boo
rearrange some #if !defined() / #else / #endif statements to remove
the negative logic.
Signed-off-by: Andrew Dyer <[EMAIL PROTECTED]>
---
drivers/video/cfb_console.c | 24
1 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/video/cfb_conso
Andrew Dyer wrote:
> 1) Change the i.MX serial driver to use the baud rate set in the
> u-boot environment
>
> 2) don't assume a 16MHz value for PERCLK1 in baud rate calculations
>
> 3) don't write a 1 to the RDR bit in the USR2 reg. (bit is not "write
> one
.gmane.org/gmane.comp.boot-loaders.u-boot/21941
and also been done for other arm cpus:
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/12390
a quick grep shows the same problem exists for
cpu/sa1100/interrupts.c, but I don't have the h/w to test it.
Signed-off-by: Andrew Dyer &l
This patch is for testing/comment - I have run it on our i.MX system,
but don't have an mx1ads, scb9328, or mx1fs2 board to play with.
1) pull common code for PLL calculations out of each function
2) add get_coreclk() to fetch the arm core frequency (we use for
printing core clock speed in check
an output. The
remaining GPIO need to be handled by board specific code to prevent
possible drive conflicts. Set as inputs for safety.
replace a few magic numbers with defines
Signed-off-by: Andrew Dyer <[EMAIL PROTECTED]>
---
drivers/net/dm9000x.c
1) Change the i.MX serial driver to use the baud rate set in the
u-boot environment
2) don't assume a 16MHz value for PERCLK1 in baud rate calculations
3) don't write a 1 to the RDR bit in the USR2 reg. (bit is not "write
one to clear" like other status bits in the reg.)
S
Code in cpu/arm920t/start.S will die with a compilation error if
CONFIG_STACKSIZE + CFG_MALLOC_LEN works out to an invalid constant for
the ARM sub instruction. Change the code so that each is subtracted
independently to avoid the error.
Signed-off-by: Andrew Dyer <[EMAIL PROTECTED]>
--
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