On 10/13/22 22:05, Icenowy Zheng wrote:
> To support SPI NAND flashes, more commands than Read (03h) are needed.
>
> Extract the code for doing SPI transfer from the reading code for code
> reuse.
>
> Signed-off-by: Icenowy Zheng
One comment below.
Reviewed-by: Samuel
Hi Andre,
On 1/11/23 17:08, Andre Przywara wrote:
> On Mon, 28 Nov 2022 00:47:55 -0600
> Samuel Holland wrote:
>
> Hi Samuel,
>
>> This driver handles most voltage regulators found in X-Powers AXP PMICs.
>> It is based on, and intended to replace, the regulator drive
h/arm/mach-sunxi/Kconfig | 27 ----
Reviewed-by: Samuel Holland
Tested-by: Samuel Holland
ange intended.
>
> Signed-off-by: Andre Przywara
> ---
> drivers/mmc/sunxi_mmc.c | 117 +---
> 1 file changed, 61 insertions(+), 56 deletions(-)
Reviewed-by: Samuel Holland
Tested-by: Samuel Holland
_cmd *cmd,
> return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
> }
>
> -static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
> -{
> - struct sunxi_mmc_priv *priv = mmc->priv;
> - int cd_pin;
> -
> - cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
> -
ensure they are as close to the end of SRAM as possible.
> Signed-off-by: Andre Przywara
> ---
> include/configs/sunxi-common.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Samuel Holland
Tested-by: Samuel Holland
nt second copy, both from the fel_stash data structure,
> and also the code saving and restoring it.
>
> Signed-off-by: Andre Przywara
> ---
> arch/arm/cpu/armv7/sunxi/fel_utils.S | 4
> arch/arm/mach-sunxi/board.c | 1 -
> 2 files changed, 5 deletions(-)
Reviewed-by: Samuel Holland
Tested-by: Samuel Holland
r storing the values.
>
> Signed-off-by: Andre Przywara
> ---
> arch/arm/cpu/armv8/fel_utils.S | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Samuel Holland
Tested-by: Samuel Holland
Hi Rick,
On 1/3/23 02:20, Rick Chen wrote:
> When fit image boots from ram, the payload will
> be prepared in the address of SPL_LOAD_FIT_ADDRESS.
> In spl fit generic flow, it will malloc another
> memory address and copy whole fit image to this
> malloc address. But it is un-necessary for booti
egion. So it is
> necessary to change openSBI address from 0x100 to 0x0.
>
> More details can refer to commit cb052d771200
> ("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+")
>
> Signed-off-by: Rick Chen
Reviewed-by: Samuel Holland
> ---
>
On 12/27/22 21:22, Rick Chen wrote:
> Hi Samuel,
>
> Samuel Holland 於 2022年12月28日 週三 上午10:47寫道：
>>
>> On 12/22/22 01:21, Rick Chen wrote:
>>> When fit image boots from ram, the payload will
>>> be prepared in the address of SPL_LOAD_FIT_ADDRESS.
>
On 12/22/22 01:21, Rick Chen wrote:
> When fit image boots from ram, the payload will
> be prepared in the address of SPL_LOAD_FIT_ADDRESS.
> In spl fit generic flow, it will malloc another
> memory address and copy whole fit image to this
> malloc address. But it is un-necessary for booting
> fro
On 12/5/22 18:45, Andre Przywara wrote:
> So far we were open-coding the pincontroller's GPIO output/input access
> in each function using that.
>
> Provide two functions that wrap that nicely, so users don't need to know
> about the internals, and we can abstract the new D1 pinctrl more easily.
>
Andre,
On 12/14/22 08:25, Andre Przywara wrote:
> On Wed, 14 Dec 2022 02:37:12 -0600 Samuel Holland wrote:
>> On 12/5/22 18:45, Andre Przywara wrote:
>>> diff --git a/configs/Sinovoip_BPI_M3_defconfig
>>> b/configs/Sinovoip_BPI_M3_defconfig
>>> index ab70e
Hi Andre,
Thanks for this cleanup! With the two issues below addressed, it looks
good to me.
On 12/5/22 18:45, Andre Przywara wrote:
> The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
> the power for the Ethernet "MAC" (mostly PHY, really).
> In the DT this is described wi
Hi Andre,
On 12/5/22 18:45, Andre Przywara wrote:
> The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that
> enables the power for a SATA harddisk.
> In the DT this is described with the target-supply property in the AHCI
> DT node, pointing to a (GPIO controlled) regulator. Since we n
27;t want to
enable CONFIG_SYS_ARCH_TIMER on sunxi SoCs where it is available. And
making this generic could eventually remove the need for the version in
arch/arm/cpu/armv7/nonsec_virt.S. But this patch is still an improvement
as-is.
Tested-by: Samuel Holland
> +obj-y+= arch_timer.o
>
11 insertions(+), 12 deletions(-)
Reviewed-by: Samuel Holland
Tested-by: Samuel Holland
ra
> ---
> board/sunxi/board.c | 4
> 1 file changed, 4 deletions(-)
Reviewed-by: Samuel Holland
Tested-by: Samuel Holland
anged, 7 insertions(+), 6 deletions(-)
Reviewed-by: Samuel Holland
Tested-by: Samuel Holland
t; For rk3xxx.dtsi:
>
> uart2: serial@20064000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x20064000 0x400>;
> interrupts = ;
> reg-shift = <2>;
> reg-io-width = <1>;
>
If the UART bus clock has a gate, it must be enabled before the UART
can be used.
Signed-off-by: Samuel Holland
---
Changes in v2:
- Only enable the first clock, as using the clk_get_bulk() API pushes
a board (phycore-rk3288) over its SPL size limit.
drivers/serial/ns16550.c | 5 +
1
On 12/12/22 12:54, Tom Rini wrote:
> On Sun, Nov 27, 2022 at 11:48:34PM -0600, Samuel Holland wrote:
>
>> If the UART bus or baud clock has a gate, it must be enabled before the
>> UART can be used.
>>
>> Signed-off-by: Samuel Holland
>> Reviewed-by: Stefan
The HDMI PHY depends on the HVCC supply being enabled. So far we have
relied on it being enabled by an earlier firmware stage (SPL or TF-A).
Attempt to enable the regulator here, so we can remove that dependency.
Signed-off-by: Samuel Holland
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 6
: Samuel Holland
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c
b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 4f5d0989286..04588b570fd 100644
--- a/drivers/video/sunxi
From: Jernej Skrabec
Currently HDMI controller MMIO address is hardcoded. Change that so
address is read from DT node. That will make adding support for new
variants a bit easier.
Signed-off-by: Jernej Skrabec
Signed-off-by: Samuel Holland
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 39
Add clock/reset definitions for display-related peripherals, including
the display engine, TCONs, and DSI and HDMI encoders, so those drivers
can be converted to DM clock consumers instead of directly manipulating
the CCU registers.
Signed-off-by: Samuel Holland
---
drivers/clk/sunxi/clk_a64.c
Skrabec
Signed-off-by: Samuel Holland
---
drivers/video/sunxi/sunxi_dw_hdmi.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c
b/drivers/video/sunxi/sunxi_dw_hdmi.c
index 19ed80b48a4..e7265af7d8f 100644
--- a/drivers/video
ec (2):
video: sunxi: dw-hdmi: Probe driver by compatible
video: sunxi: dw-hdmi: Read address from DT node
Samuel Holland (3):
clk: sunxi: Add DE2 display-related clocks/resets
video: sunxi: dw-hdmi: Use DM for clock gates and resets
video: sunxi: dw-hdmi: Use DM for HVCC regulator
dr
- LDOs shared with GPIO pins => not supported.
Signed-off-by: Samuel Holland
---
drivers/power/regulator/Kconfig | 14 ++
drivers/power/regulator/Makefile| 1 +
drivers/power/regulator/axp_regulator.c | 308
3 files changed, 323 insertions(+)
create
Now that a regulator driver exists for this PMIC, hook it up to the
device tree "regulators" subnodes.
Signed-off-by: Samuel Holland
---
drivers/power/pmic/axp.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/power/pmic/axp.c b/drivers/power/pmic/a
Subordinate regulator drivers can use this enumerated ID instead of
matching the compatible string again.
Signed-off-by: Samuel Holland
---
drivers/power/pmic/axp.c | 18 +-
include/axp_pmic.h | 12
2 files changed, 21 insertions(+), 9 deletions(-)
diff
t was convenient to initialize the PMIC at the time.
The main goal here is to replace the corresponding code in TF-A, both
because of TF-A size constraints, and because the TF-A code is too
simple/overzealous and breaks EPHY power sequencing on some boards.
Samuel Holland (3):
power: pmic: axp: Prov
This allows devm_reset_control_get(dev, NULL) to work and get the first
reset control, which is common in code ported from Linux.
Signed-off-by: Samuel Holland
---
drivers/reset/reset-uclass.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/reset/reset-uclass.c
This allows devm_clock_get(dev, NULL) to work and get the first clock,
which is common in code ported from Linux.
Signed-off-by: Samuel Holland
---
drivers/clk/clk-uclass.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk
If the UART bus or baud clock has a gate, it must be enabled before the
UART can be used.
Signed-off-by: Samuel Holland
---
drivers/serial/ns16550.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 7592979cab5..785fb520062
in the legacy clock/reset bindings is the register bit
offset, so the drivers are trivial. Only the outer PRCM node has a reg
property, so the clock/reset drivers use the parent device's MMIO base.
Signed-off-by: Samuel Holland
---
I didn't reuse the sunxi gate/reset ops, because the
P2WI and RSB are used to communicate with a PMIC. Most SoCs have only
one possible pinmux. F1C100s has two possibilities, with different mux
values, so omit it until some board needs one of them.
Signed-off-by: Samuel Holland
---
Changes in v2:
- Fix pin list comment for A80 entry
drivers
P2WI and RSB are used to communicate with a PMIC. Most SoCs have only
one possible pinmux. F1C100s has two possibilities, with different mux
values, so omit it until some board needs one of them.
Signed-off-by: Samuel Holland
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 7 +++
1 file
Hi Simon,
On 11/7/22 17:35, Simon Glass wrote:
> Hi Samuel,
>
> On Mon, 31 Oct 2022 at 13:27, Simon Glass wrote:
>>
>> On Sun, 30 Oct 2022 at 21:41, Samuel Holland wrote:
>>>
>>> reg must contain enough cells for the entire next address/size pair
>>
but it is not guaranteed to
work. Underscores are allowed even between single-letter extensions. See
section 29.5 ("Underscores") of the unprivileged spec. Still, this is an
improvement, so:
Reviewed-by: Samuel Holland
> + for (i = 4; i < sizeof(desc);
On 11/3/22 11:46, Andre Przywara wrote:
> On Tue, 1 Nov 2022 00:08:12 -0500
> Samuel Holland wrote:
>
> Hi Samuel,
>
>> sunxi is getting a new RISC-V platform, D1. We want to share as much of
>> the existing configuration as possible, to provide a familiar
On 11/4/22 06:21, Yu Chien Peter Lin wrote:
> We should check the string until it hits underscore, in case it
> searches for the letters in the custom extension. For example,
> "rv64imac_xandes" will be treated as D extension support since
> there is a "d" in "andes", resulting illegal instruction
Hi all,
Thanks for CCing me, Andre.
On 11/1/22 13:15, Andre Przywara wrote:
> On Mon, 31 Oct 2022 15:43:01 -0400
> Tom Rini wrote:
>
> Hi Tom, Simon,
>
>> On Mon, Oct 31, 2022 at 01:27:06PM -0600, Simon Glass wrote:
>>> Hi Tom,
>>>
>>> On Sun, 30 Oct 2022 at 11:53, Tom Rini wrote:
This provides a unified configuration across all sunxi boards,
regardless of CPU architecture.
Signed-off-by: Samuel Holland
---
disk/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/disk/Kconfig b/disk/Kconfig
index c9b9dbaf1a..b9d3625dc2 100644
--- a/disk
This provides a unified configuration across all sunxi boards,
regardless of CPU architecture.
Signed-off-by: Samuel Holland
---
common/spl/Kconfig | 12 ++--
scripts/Makefile.spl | 2 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/common/spl/Kconfig b/common/spl
This provides a unified configuration across all sunxi boards,
regardless of CPU architecture.
Signed-off-by: Samuel Holland
---
drivers/clk/sunxi/Kconfig | 2 +-
drivers/fastboot/Kconfig | 13 ++---
drivers/gpio/Kconfig | 2 +-
drivers/mmc/Kconfig | 2
This ensures the same environment layout will be used across all sunxi
boards, regardless of CPU architecture.
Signed-off-by: Samuel Holland
---
env/Kconfig | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/env/Kconfig b/env/Kconfig
index 24111dfaf4..ae28e4e3e6
This excludes options that are inherently ARM-specific or are specific
to legacy non-DM drivers.
Some help text is cleaned up along the way.
Signed-off-by: Samuel Holland
---
arch/arm/mach-sunxi/Kconfig | 71
board/sunxi/Kconfig | 72
This is how the vast majority of platforms provided TEXT_BASE.
sunxi was the exception here.
Signed-off-by: Samuel Holland
---
board/sunxi/Kconfig | 6 ++
boot/Kconfig| 4
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
It makes sense to put this near the definition of SUNXI_SRAM_ADDRESS.
Signed-off-by: Samuel Holland
---
board/sunxi/Kconfig | 5 +
common/spl/Kconfig | 3 ---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 1abb3e1816
This will provide a default value for RISC-V when that is added, and it
makes sense to put this option next to the other DRAM layout options.
Signed-off-by: Samuel Holland
---
Kconfig | 3 ---
board/sunxi/Kconfig | 5 +
2 files changed, 5 insertions(+), 3 deletions(-)
diff
This provides a default value for RISC-V when that is added, and it
makes sense to put this option next to the other DRAM layout options.
While at it, provide sensible values for platforms with less DRAM.
Signed-off-by: Samuel Holland
---
board/sunxi/Kconfig | 6 ++
common/spl/Kconfig
This provides a default value for RISC-V when that is added, and it
makes sense to put this option next to the other DRAM layout options.
While at it, provide sensible values for platforms with less DRAM.
Signed-off-by: Samuel Holland
---
board/sunxi/Kconfig | 6 ++
common/Kconfig
Update this option to be based on SUNXI_MINIMUM_DRAM_MB. This corrects
the value used on V3s, which previously was the MACH_SUN8I default, and
so relied on addresses wrapping modulo the DRAM size.
Signed-off-by: Samuel Holland
---
board/sunxi/Kconfig | 9 ++---
1 file changed, 2 insertions
This option affects the ABI between SPL/U-Boot and U-Boot/scripts, so it
should not normally be changed by the user.
Signed-off-by: Samuel Holland
---
board/sunxi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index
This keeps all of the defaults for sunxi platforms in one place. Most of
these only depend on architecture-independent features of the SoC (clock
tree or SRAM layout) anyway.
No functional change; just some minor help text cleanup.
Signed-off-by: Samuel Holland
---
arch/arm/mach-sunxi/Kconfig
This is used by quite a large number of boards, for PMIC/regulator or
LCD panel control.
Signed-off-by: Samuel Holland
---
board/sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index b301ba998e..809cd17f54 100644
--- a/board/sunxi
While not especially likely, it is plausible that someone wants to build
U-Boot without GPIO or UART support. Don't force building these drivers.
Signed-off-by: Samuel Holland
---
board/sunxi/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/sunxi/Kcon
This was already supported by every machine type. It is unlikely that
any new SoC support will be added without SPL support.
Signed-off-by: Samuel Holland
---
arch/arm/mach-sunxi/Kconfig | 14 --
board/sunxi/Kconfig | 2 ++
2 files changed, 2 insertions(+), 14 deletions
To maintain consistent behavior across architectures, most of the
options selected by ARCH_SUNXI should be selected for the D1 SoC as
well. To accomplish this, select them from BOARD_SUNXI instead.
No functional change here. Lines are only moved and alphabetized.
Signed-off-by: Samuel Holland
ot;if ARCH_SUNXI" block.
Introduce a new BOARD_SUNXI symbol that can be selected by both
ARCH_SUNXI now and the new RISC-V SoC symbols when they are added, and
use it to gate the architecture-independent board options.
Signed-off-by: Samuel Holland
---
arch/Kconfig| 1 +
This choice is meaningless when SPL is disabled. Hide it to avoid any
possible confusion.
Signed-off-by: Samuel Holland
---
board/sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 084a8b0c6c..42f61df5c5 100644
--- a/board/sunxi
Some of the selected symbols have a user-visible dependency. Make the
selections conditional on that dependency to avoid creating invalid
configurations.
Signed-off-by: Samuel Holland
---
arch/arm/Kconfig | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch
Two of these selections are redundant and have no effect:
- DM_KEYBOARD is selected by USB_KEYBOARD
- DM_MMC is selected by MMC
This selection has no effect by default and is unnecessarily strong:
- USB_STORAGE is implied by DISTRO_DEFAULTS
Signed-off-by: Samuel Holland
---
arch/arm
respect it.
Samuel Holland (22):
sunxi: Fix default-enablement of USB host drivers
sunxi: Remove unnecessary Kconfig selections
sunxi: Add missing dependencies to Kconfig selections
sunxi: Hide image type selection if SPL is disabled
sunxi: Share the board Kconfig across architectures
s
We tried to enable USB_EHCI_GENERIC and USB_OHCI_GENERIC by default.
This did not work because those symbols depend on USB_EHCI_HCD and
USB_OHCI_HCD, which were not enabled. Fix this by implying all four.
Signed-off-by: Samuel Holland
---
arch/arm/Kconfig | 4
drivers/usb/host
With one exception (sun9i), all sunxi SoCs released to date use variants
of the same USB PHY. Instead of requiring each new SoC to duplicate the
PHY driver selection, enable it by default.
Signed-off-by: Samuel Holland
---
arch/arm/mach-sunxi/Kconfig | 11 ---
drivers/phy/allwinner
The code for these two options depends on having the FIT loadables
recorded in the FDT. Thus, these options require the full version of
the SPL_LOAD_FIT code.
Signed-off-by: Samuel Holland
---
common/spl/Kconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/common/spl
The struct is only used to overlay the MMIO region, so the behavior is
the same. This obsoletes the Kconfig option for the number of ports.
Signed-off-by: Samuel Holland
---
configs/arbel_evb_defconfig| 1 -
configs/at91sam9260ek_dataflash_cs0_defconfig | 1 -
configs
reg must contain enough cells for the entire next address/size pair
after skipping `index` pairs. The previous code allows an out-of-bounds
read when na + ns > 1.
Fixes: 69b41388ba45 ("dm: core: Add a new api to get indexed device address")
Signed-off-by: Samuel Holland
---
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Heinrich Schuchardt
> Cc: Samuel Holland
> Cc: Simon Glass
> ---
> common/board_r.c | 3 ---
> common/spl/spl.c | 3 ---
> doc/README.gpio| 6 ++
> drivers/gpio/gpio-uclass.c
Hi Andre,
On 7/18/22 11:20 AM, Andre Przywara wrote:
> P.S.: I see that the A83T kernel pinctrl driver uses "nand" for *some* pins
> instead of "nand0", not sure if that should to be fixed, or if it's too
> late for that (not that NAND is mentioned at all in the A83T DT files ...)
I already sent
On 7/18/22 11:10 AM, Andre Przywara wrote:
> On Wed, 13 Jul 2022 22:15:21 -0500
> Samuel Holland wrote:
>
> Hi,
>
>> Currently NAND clock setup is done in board code, both in SPL and in
>> U-Boot proper. Add the NAND clocks/resets here so they can be used by
>>
tools: relocate-rela: Read rela start/end directly from
ELF")
Fixes: a1405d9cfedb ("tools: relocate-rela: Check that relocation works only
for EM_AARCH64")
Signed-off-by: Samuel Holland
---
tools/relocate-rela.c | 125 +++---
1 file changed,
This header is not used since commit abdbefba2a4e ("net: sun8i_emac: Use
consistent clock bitfield definitions"). Dropping it allows the driver
to be architecture-independent.
Signed-off-by: Samuel Holland
---
drivers/net/sun8i_emac.c | 1 -
1 file changed, 1 deletion(-)
diff --git
efits beyond the simplification:
- R40 boards now respect the RX delays from the devicetree
- This resolves a warning on architectures where readl/writel
expect the address to have a pointer type, not phys_addr_t.
Signed-off-by: Samuel Holland
---
drivers/net/sun8i_emac.c
This just prints the PHY mode taken from the devicetree. It does not
need to be printed during every boot.
Signed-off-by: Samuel Holland
---
drivers/net/sun8i_emac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index
D1 is a RISC-V SoC containing an EMAC compatible with the A64 EMAC.
However, there are a couple of issues with the driver preventing it
being built for RISC-V. These are resolved by patches 2-3. Patch 1 is
a general cleanup.
Samuel Holland (3):
net: sun8i-emac: Downgrade printf during probe to
t; variables and symbols.
While we are at it, generalise the existing code by allowing a bitmap
of bits to clear and set, to cover newer SoCs: The A100 and H616 use a
different bit for the SIDDQ control.
Signed-off-by: Andre Przywara
Signed-off-by: Samuel Holland
---
drivers
Since commit 089ffd0aedb7 ("phy: sun4i-usb: Use CLK and RESET support")
neither of these headers is used. Dropping them allows the driver to be
architecture-independent.
Signed-off-by: Samuel Holland
---
drivers/phy/allwinner/phy-sun4i-usb.c | 2 --
1 file changed, 2 deletions(-)
di
D1 has a register layout like A100 and H616, with the moved SIDDQ bit.
Unlike H616 it does not have any dependencies between PHY instances.
Signed-off-by: Samuel Holland
---
drivers/phy/allwinner/phy-sun4i-usb.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/phy
This option is used only by the phy-sun4i-usb driver, which does not
inherently depend on the ARM architecture.
Signed-off-by: Samuel Holland
---
arch/arm/mach-sunxi/Kconfig | 9 -
drivers/phy/allwinner/Kconfig | 10 ++
2 files changed, 10 insertions(+), 9 deletions(-)
diff
driver.
After this series, the driver still uses the VBUS and ID pin options
from arch/arm/mach-sunxi/Kconfig. Those options will be replaced by
devicetree properties in a separate series.
Andre Przywara (1):
phy: sun4i-usb: Rework HCI PHY (aka "pmu_unk1") handling
Samuel Holland (3
Now that the PHY driver will not try to drive VBUS if it is already
driven by an external supply, there is no need to check the VBUS voltage
before powering on the PHY.
Signed-off-by: Samuel Holland
---
drivers/usb/musb-new/sunxi.c | 6 --
1 file changed, 6 deletions(-)
diff --git a
matches the Linux PHY driver.
Signed-off-by: Samuel Holland
---
drivers/phy/allwinner/phy-sun4i-usb.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index aef2cb8f6f82..e1b01e732515 100644
--- a/drivers/phy
Clocks, resets, and pinmuxes are now handled by the driver model, so the
only thing the "board" code needs to do is load the driver. This matches
the pattern used by other DM raw NAND drivers (there is no NAND uclass).
The actual board code is now only needed in SPL.
Signed-off-
This more closely matches the U-Boot driver to the Linux version.
Signed-off-by: Samuel Holland
---
drivers/mtd/nand/raw/sunxi_nand.c | 39 ---
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/mtd/nand/raw/sunxi_nand.c
b/drivers/mtd/nand/raw
: Samuel Holland
---
drivers/mtd/nand/raw/sunxi_nand.c | 73 +++
include/fdtdec.h | 1 -
lib/fdtdec.c | 1 -
3 files changed, 26 insertions(+), 49 deletions(-)
diff --git a/drivers/mtd/nand/raw/sunxi_nand.c
b/drivers/mtd/nand/raw
Each chip is required to have a unique CS number ("reg" property) in the
range 0-7, so there is no need to separately count the number of chips.
Signed-off-by: Samuel Holland
---
drivers/mtd/nand/raw/sunxi_nand.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/driver
This series converts the sunxi NAND driver to get its resources (clocks,
resets, pins) from the devicetree, and probe using the driver model.
In addition to the immediate cleanup, this allows backporting more
patches (bugfixes, newer SoC support) from the Linux driver.
Samuel Holland (6):
clk
NAND is always at function 2 on port C.
Pin lists and mux values were taken from the Linux drivers.
Signed-off-by: Samuel Holland
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
b/drivers
Currently NAND clock setup is done in board code, both in SPL and in
U-Boot proper. Add the NAND clocks/resets here so they can be used by
the "full" NAND driver once it is converted to the driver model.
The bit locations are copied from the Linux CCU drivers.
Signed-off-by: Samu
Hi Michal,
On 7/3/22 2:20 PM, Michal Suchanek wrote:
>
> Hello,
>
> many ARM SoCs have a mask rom feature that provides interface for
> downloading firmware over USB.
>
> Downstream rockchip u-boot has 'brom' or 'rbrom' command for this
> purpose, and downstream sunxi u-boot provides 'efex' com
Hi Andre,
On 6/27/22 7:40 PM, Andre Przywara wrote:
> On Mon, 9 May 2022 00:29:30 -0500
> Samuel Holland wrote:
>
> Hi Samuel,
>
>> This series fixes an issue with out-of-bounds access to the gate array
>> (patches 1-2), uses the rearranged array size informat
Hi Andre,
On 6/24/22 11:12 AM, Andre Przywara wrote:
> From: Samuel Holland
>
> Commit e42dad4168fe ("sunxi: use boot source for determining environment
> location") changed our implementation of env_get_location() and enabled
> it for every board, even those with
Hi Andre,
>>> On 4/20/22 7:34 PM, Andre Przywara wrote:
Commit e42dad4168fe ("sunxi: use boot source for determining environment
location") changed our implementation of env_get_location() and enabled
it for every board, even those without MMC support (like the C.H.I.P.
board
On 6/8/22 4:46 AM, Andre Przywara wrote:
> On Tue, 7 Jun 2022 21:07:59 -0500
> Samuel Holland wrote:
>
> Hi,
>
>> On 6/7/22 7:06 PM, Andre Przywara wrote:
>>> The Allwinner USB PHY driver is still using the legacy GPIO interface,
>>> which is now impl
ch need to toggle the VBUS supply
> via a GPIO, like the Teres-I laptop or the BananaPi M2 Berry board.
>
> Signed-off-by: Andre Przywara
> Reported-by: Milan P. Stanić
Reviewed-by: Samuel Holland
It looks like the other users of sunxi_name_to_gpio are unaffected because they
call onl
Copy the devicetree source for the A10 SoC and all existing boards
verbatim from the Linux v5.18-rc1 tag.
The previous version of this change was only partially applied.
Fixes: 4746694cba74 ("ARM: dts: sun4i: Sync from Linux v5.18-rc1")
Signed-off-by: Samuel Holland
---
Cha
101 - 200 of 614 matches
Mail list logo
