Hi Felipe,
On Jun 10, 2014 11:45 AM, "Felipe Balbi" wrote:
>
> pass correct PHY Address when running on SK
> so that we have working ethernet with this board
> too.
>
> Signed-off-by: Felipe Balbi
> ---
> board/ti/am43xx/board.c | 21 +
> 1 file changed, 13 insertions(+), 8
WT:A)
> GP EVM:
> OSC clk : 24MHz
> DDR : DDR3 @ 400MHz(MT41K512M8RH)
>
> This patch series is applied on top of Mainline U-Boot Tree and two
> patches mentioned below:
> git://git.denx.de/u-boot.git master
>http://patchwork.ozlabs.org/patch/288175/
>
On Sun, Dec 1, 2013 at 11:21 PM, Lokesh Vutla wrote:
][...]
> We should not rely on RTC here. I don't think U-Boot should worry about low
> power state. You mean to
> say about passing this information to kernel?
No. I am not asking you to pass this to the kernel.
> In the current kernel also m
On Sun, Dec 1, 2013 at 10:53 PM, Lokesh Vutla wrote:
[...]
> I read more about it and got inputs from Sekhar. I came to know that there is
> a DEV_ATTRIBUTE register
> which tells about the safest OPP to boot with. Looks like this should be
> sufficient to get the values.
> Ill add this code and
On Wed, Nov 27, 2013 at 4:34 AM, Lokesh Vutla wrote:
[...]
> Ideally the default value should be exported from e-fuse values.
> EMIF does some HW sequence according to the value exported here. This filed
> tells
> what type of memory it is.
>
No, eFuse is not the right place for this information
On Wed, Nov 27, 2013 at 1:58 AM, Lokesh Vutla wrote:
> On Wednesday 27 November 2013 05:36 AM, Vaibhav Bedia wrote:
>> On Mon, Nov 25, 2013 at 12:08 AM, Lokesh Vutla wrote:
>>> On Friday 22 November 2013 02:07 AM, Vaibhav Bedia wrote:
>>>> On Thu, Nov 21, 2013 a
On Mon, Nov 25, 2013 at 12:18 AM, Lokesh Vutla wrote:
> On Friday 22 November 2013 02:22 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
>> [...]
>>
>>> -/*
>>> - * Get SDRAM type connected to EMIF.
>>> - * As
On Mon, Nov 25, 2013 at 12:13 AM, Lokesh Vutla wrote:
> On Friday 22 November 2013 02:16 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
>>> AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
>>> Adding LPDDR2 init sequen
On Mon, Nov 25, 2013 at 12:08 AM, Lokesh Vutla wrote:
> On Friday 22 November 2013 02:07 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
>>> Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
>>> Following are the
On Sun, Nov 24, 2013 at 11:59 PM, Lokesh Vutla wrote:
> On Friday 22 November 2013 02:04 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
>>> Updating the mux data for UART, adding data for i2c0 and mmc.
>>> And also updating pad_signal
On Sun, Nov 24, 2013 at 11:53 PM, Lokesh Vutla wrote:
> On Friday 22 November 2013 02:01 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
>>> Selecting the Master osc clk as Timer2 clock source.
>>>
>>> Signed-off-by: Lokesh Vu
On Sun, Nov 24, 2013 at 11:48 PM, Lokesh Vutla wrote:
> On Friday 22 November 2013 01:58 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
>> [...]
>>> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
>>> + char safe_string[HDR_
On Sun, Nov 24, 2013 at 11:46 PM, Lokesh Vutla wrote:
> On Friday 22 November 2013 01:56 AM, Vaibhav Bedia wrote:
>> On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
>> [...]
>>> #define NON_SECURE_SRAM_START 0x402F0400
>>> #define NON_SECURE_SR
On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
[...]
> -/*
> - * Get SDRAM type connected to EMIF.
> - * Assuming similar SDRAM parts are connected to both EMIF's
> - * which is typically the case. So it is sufficient to get
> - * SDRAM type from EMIF1.
> - */
> -u32 emif_sdram_type()
> -{
On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
> AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
> Adding LPDDR2 init sequence and register details for the same.
> Below is the brief description of LPDDR2 init sequence:
> -> Configure VTP
> -> Configure DDR IO settings
> ->
On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
[...]
> +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
> + char safe_string[HDR_NAME_LEN + 1];
> + struct am43xx_board_id header;
> +
> + if (read_eeprom(&header) < 0)
> + puts("Could not get board ID.\n");
Hmm...
On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
> Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
> Following are the DPLL locking frequencies at OPP NOM:
> MPU locks at 600MHz
> Core locks at 1000MHz
> Per locks at 960MHz
> DDR locks at 266MHz
>
As mentioned earlier,
On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
> Updating the mux data for UART, adding data for i2c0 and mmc.
> And also updating pad_signals structure.
>
> Signed-off-by: Lokesh Vutla
> ---
> arch/arm/include/asm/arch-am33xx/mux_am43xx.h | 45
> +
> board/ti/am
On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
> Selecting the Master osc clk as Timer2 clock source.
>
> Signed-off-by: Lokesh Vutla
> ---
> arch/arm/cpu/armv7/am33xx/clock_am43xx.c |4
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
>
On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
[...]
> #define NON_SECURE_SRAM_START 0x402F0400
> #define NON_SECURE_SRAM_END0x4034
> #define SRAM_SCRATCH_SPACE_ADDR0x4033C000
> +#define AM4372_BOARD_NAME_STARTSRAM_SCRATCH_SPACE_ADDR
> +#define AM4372_BOARD_NAME_E
Hi Lokesh,
On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla wrote:
[...]
> +#define CM_DPLL0x44DF4200
> +#define CM_RTC 0x44df8500
>
nit: CM_RTC address should be in caps for the sake of consistency
> #define PRM_RSTCTRL(
Hi,
On Thu, Nov 7, 2013 at 4:16 PM, Tom Rini wrote:
>
> It's an open question on if TI81xx needs these set or was simply also
> setting them for historical reasons (and in turn was inherited by am335x).
>
Based on Matt's test TI814x looks ok. I recall putting this code there
for PG1.0 of TI8168
Hi Sekhar :)
On Wed, Nov 13, 2013 at 11:08 AM, Sekhar Nori wrote:
> Hi Vaibhav,
>
> On 11/13/2013 7:38 PM, Vaibhav Bedia wrote:
>> On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla wrote:
>> [...]
>>> I checked with hardware folks. There is no register or some way to
On Wed, Nov 13, 2013 at 3:48 AM, Lokesh Vutla wrote:
[...]
> I checked with hardware folks. There is no register or some way to tell
> if VTT is present. It is not added in EEPROM also and I have no answer why it
> is not added in EEPROM..:(
> It is specific to boards using DDR3. So its good to ha
On Thu, Nov 7, 2013 at 4:06 PM, Tom Rini wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 11/07/2013 03:56 PM, Vaibhav Bedia wrote:
>> Hi Tom,
>>
>> On Wed, Nov 6, 2013 at 4:37 PM, Tom Rini wrote:
>>>>>>> +
>>>>>
Hi Tom,
On Thu, Nov 7, 2013 at 11:42 AM, Tom Rini wrote:
> Based on the definitive guide to EMIF configuration[1] certain registers
> that we have been modifying (and are documented registers) should be
> left in their reset values rather than modified. This has been tested
> on AM335x GP EVM an
Hi Lokesh,
On Thu, Nov 7, 2013 at 8:43 AM, Lokesh Vutla wrote:
> Hi Vaibhav,
> On Wednesday 06 November 2013 06:10 PM, Vaibhav Bedia wrote:
>> On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
>>> Selecting the Master osc clk as Timer2 clock source.
>>
>> I
Hi Tom,
On Wed, Nov 6, 2013 at 4:37 PM, Tom Rini wrote:
> +
> + if (header->magic != 0xEE3355AA) {
Why is the header the same as AM335x? Shouldn't it be something
like 0xEE3344AA or whatever?
>>> No, the header is still same. It is 0xEE3355AA.
>>>
>>
>> My question wa
On Wed, Nov 6, 2013 at 8:54 AM, Lokesh Vutla wrote:
> On Wednesday 06 November 2013 06:32 PM, Vaibhav Bedia wrote:
>> On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
>>> GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C).
>>> Adding details for the s
On Wed, Nov 6, 2013 at 8:45 AM, Lokesh Vutla wrote:
> On Wednesday 06 November 2013 06:27 PM, Vaibhav Bedia wrote:
>> On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
>>> AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
>>> Adding LPDDR2 init sequen
On Wed, Nov 6, 2013 at 8:32 AM, Lokesh Vutla wrote:
> On Wednesday 06 November 2013 06:13 PM, Vaibhav Bedia wrote:
>> On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
>>> Updating the mux data for UART, and adding data for i2c0 and mmc.
>>>
>>> Signed-off
On Wed, Nov 6, 2013 at 8:25 AM, Lokesh Vutla wrote:
> On Wednesday 06 November 2013 06:08 PM, Vaibhav Bedia wrote:
>> On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
>>> From: Sekhar Nori
>>>
>>> Add support for reading onboard EEPROM to enable
>&g
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
> GP EVM has 1GB DDR3 attached(Part no: MT47H128M16RT-187E:C).
> Adding details for the same.
> Below is the brief description of DDR3 init sequence(SW leveling):
> -> Enable VTT regulator
> -> Configure VTP
> -> Configure DDR IO settings
> -> D
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
> AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
> Adding LPDDR2 init sequence and register details for the same.
> Below is the brief description of LPDDR2 init sequence:
> -> Configure VTP
> -> Configure DDR IO settings
> ->
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
> Adding DPLLs Multiplier and DIvider values for GP EVM
> Following are the DPLL locking frequencies at OPP NOM
> MPU locks at 600MHz
> Core locks at 1000MHz
> Per locks at 960MHz
> DDR locks at 400MHz
>
Comment on getting the data from eFuse o
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
> Updating the Multiplier and Dividers values for all DPLLs for EPOS EVM.
> Following are the DPLL locking frequencies at OPP NOM:
> MPU locks at 600MHz
> Core locks at 1000MHz
> Per locks at 960MHz
> DDR locks at 266MHz
>
Why is this not readi
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
> Updating the mux data for UART, and adding data for i2c0 and mmc.
>
> Signed-off-by: Lokesh Vutla
> ---
> arch/arm/include/asm/arch-am33xx/mux_am43xx.h |4 +++-
> board/ti/am43xx/mux.c | 24 +
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
> Selecting the Master osc clk as Timer2 clock source.
I obviously missed the first round of patches for AM43xx here. Why is
timer2 being used here? Don't we use the synctimer and timer1 in the kernel?
Regards,
Vaibhav
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
> From: Sekhar Nori
>
> Add support for reading onboard EEPROM to enable
> board detection.
>
> Signed-off-by: Sekhar Nori
> Signed-off-by: Lokesh Vutla
> ---
> arch/arm/include/asm/arch-am33xx/omap.h |2 ++
> board/ti/am43xx/board.c
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
> Use ti_armv7_common.h config file to inclde the common
> configs.
[...]
> +/* Clock Defines */
> +#define V_OSCK 2400 /* Clock output from T2 */
> +#define V_SCLK (V_OSCK)
I know this is
HI Lokesh :)
On Mon, Nov 4, 2013 at 11:20 PM, Lokesh Vutla wrote:
> PRCM, timer base addresses and offsets are different from
> AM33xx. Updating the same.
>
> Signed-off-by: Lokesh Vutla
> ---
> arch/arm/include/asm/arch-am33xx/cpu.h | 17 +++--
> arch/arm/include/asm/
Hi Heiko,
On Mon, Nov 4, 2013 at 10:30 PM, Heiko Schocher wrote:
> Hello Vaibhav Bedia,
>
> Am 04.11.2013 20:45, schrieb Vaibhav Bedia:
>
>> Hi Marek,
>>
>> On Mon, Nov 4, 2013 at 12:34 PM, Marek Vasut wrote:
>>>
>>> Dear Vaibhav Bedia,
>>
Hi Marek,
On Mon, Nov 4, 2013 at 12:34 PM, Marek Vasut wrote:
> Dear Vaibhav Bedia,
>
>> On Mon, Nov 4, 2013 at 8:15 AM, Heiko Schocher wrote:
>> [...]
>>
>> > Hups, missed this EMail ... :-(
>>
>> No problem. Happens all the time :)
>>
>>
On Mon, Nov 4, 2013 at 8:15 AM, Heiko Schocher wrote:
[...]
> Hups, missed this EMail ... :-(
>
No problem. Happens all the time :)
> Hmm.. some boards from siemens do not use the RTC, so this approach
> is not possible here ...
>
By unused do you mean it's not powered up or is it simply not pr
Hi Heiko,
On Mon, Nov 4, 2013 at 2:02 AM, Heiko Schocher wrote:
> Patch 1 introduces bootcount support for the 3 siemens boards. As there
> is no other possibility on this boards, the bootcounter is stored in the
> environment. To prevent a "saveenv" on all reboots, a "upgrade_available"
> U-Boot
Hi Heiko,
On Tue, Oct 22, 2013 at 6:25 AM, Heiko Schocher wrote:
> If no softreset save registers are found on the hardware
> "bootcount" is stored in the environment. To prevent a
> saveenv on all reboots, the environment variable
> "upgrade_available" is introduced. If "upgrade_available" is
>
On Wed, Oct 20, 2010 at 10:46 AM, Mike Frysinger wrote:
> On Wednesday, October 20, 2010 00:38:08 Vaibhav Bedia wrote:
>
> please do not top post
>
> Sorry about the top posting.
> > The size of other sections like the bss section also need to be accounted
> >
Hi,
The size of other sections like the bss section also need to be accounted
for when doing a size check.
Insufficient space for bss when doing something like a MMC read which
requires large buffers causes system hangs for no apparent reason.
Regards,
Vaibhav
On Wed, Oct 20, 2010 at 2:59 AM, W
On Tue, Sep 14, 2010 at 7:03 PM, V, Aneesh wrote:
> Hi,
>
> > -Original Message-
> > From: u-boot-boun...@lists.denx.de [mailto:u-boot-
> > boun...@lists.denx.de] On Behalf Of Vipin Kumar
> > Sent: Tuesday, September 14, 2010 3:52 PM
> > To: Stefan Roese
> > Cc: u-boot@lists.denx.de; Shir
[...]
> +/**
> + * @brief board_init
> + *
> + * @return 0
> + */
> +int board_init(void)
> +{
> + DECLARE_GLOBAL_DATA_PTR;
> +
>
This should also be made global.
[...]
--
Regards,
Vaibhav
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists
On Tue, Jun 15, 2010 at 10:09 AM, Steve Sakoman wrote:
> +
>
[...]
> +/* Declare the global data pointer - gd */
> +DECLARE_GLOBAL_DATA_PTR;
> +
>
Once the declaration in /board/ti/sdp4430/sdp.c is made global this won't be
needed.
[...]
--- a/arch/arm/cpu/armv7/omap3/reset.S
> +++ b/arch/arm/c
On Tue, Jun 15, 2010 at 10:09 AM, Steve Sakoman wrote:
[...]
> +int board_init(void)
> +{
> + DECLARE_GLOBAL_DATA_PTR;
>
This should be moved outside the function. Relevant thread
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/31805
[...]
--
Regards,
Vaibhav
On Fri, Apr 9, 2010 at 4:59 PM, Nishanth Menon wrote:
> On 04/08/2010 08:43 AM, Rabin Vincent wrote:
> > Add Cortex A9 support by copying the code for Cortex A8. The only
> > change is a removal of some OMAP3 specific code.
> Thanks :), I was hoping to help in the near future by adding OMAP4 code
53 matches
Mail list logo
