On Mon, 29 May 2023 18:58:54 -0600
Sam Edwards wrote:
Hi Sam,
> On 5/26/23 20:15, Sam Edwards wrote:
> > My "no success" is Linux stalling indefinitely at:
> > [ 0.123090] smp: Bringing up secondary CPUs ...
>
> OK, correction: my "no success" was Linux being unable to access the
> GIC, s
Hey again Andre,
On 5/26/23 20:15, Sam Edwards wrote:
My "no success" is Linux stalling indefinitely at:
[ 0.123090] smp: Bringing up secondary CPUs ...
OK, correction: my "no success" was Linux being unable to access the
GIC, so boot was getting stuck. This was because it was running in
Hey Andre,
On 5/26/23 16:07, Andre Przywara wrote:
So with "no success" you are referring to the patch below? Which is the
Linux patch ported to U-Boot? And does that mean that the Linux patch
works, but the U-Boot version doesn't?
Yes, the diff below is what I've been trying to use. It's not
On Fri, 26 May 2023 14:22:29 -0600
Sam Edwards wrote:
Hi Sam,
> On 5/26/23 13:27, Maksim Kiselev wrote:
> >
> > There is a Linux patch that allows to bring up the second core.
> > https://github.com/szemzoa/awboot/blob/6ea4ae4ad7a558ad952fefee1942e260aea1a69f/linux/second_core_support_in_platsm
Hi folks,
On 5/26/23 13:27, Maksim Kiselev wrote:
There is a Linux patch that allows to bring up the second core.
https://github.com/szemzoa/awboot/blob/6ea4ae4ad7a558ad952fefee1942e260aea1a69f/linux/second_core_support_in_platsmp.patch#L10
I think this could be useful for adding PSCI support
Hi Sam, Andre,
On Thu, 25 May 2023 18:34:45 -0600 Sam Edwards wrote:
PS: Do you have any plans for PSCI support, so we can get the second
core up too? I'd like to patch that in and include it in your series
once my available time permits. Just thought I'd check that you/someone
wasn't working
On Thu, 25 May 2023 18:34:45 -0600
Sam Edwards wrote:
Hi Sam,
thanks for staying on this!
> On 12/5/22 17:45, Andre Przywara wrote:
> > +static struct ccu_clk_gate d1_gates[] = {
> > + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
> > + [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
> > +
Hi again Andre,
On 12/5/22 17:45, Andre Przywara wrote:
+static struct ccu_clk_gate d1_gates[] = {
+ [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
+ [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
+ [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
+ [CLK_BUS_UART0]
On Sun, 21 May 2023 21:57:57 -0600
Sam Edwards wrote:
Hi Sam,
> On 12/5/22 17:45, Andre Przywara wrote:
> > From: Samuel Holland
> >
> > Since the D1 CCU binding is defined, we can add support for its
> > gates/resets, following the pattern of the existing drivers.
> >
> > Signed-off-by: Samu
On 12/5/22 17:45, Andre Przywara wrote:
From: Samuel Holland
Since the D1 CCU binding is defined, we can add support for its
gates/resets, following the pattern of the existing drivers.
Signed-off-by: Samuel Holland
Reviewed-by: Andre Przywara
Acked-by: Sean Anderson
Hi Andre,
So far so
From: Samuel Holland
Since the D1 CCU binding is defined, we can add support for its
gates/resets, following the pattern of the existing drivers.
Signed-off-by: Samuel Holland
Reviewed-by: Andre Przywara
Acked-by: Sean Anderson
---
drivers/clk/sunxi/Kconfig | 6 +
drivers/c
11 matches
Mail list logo
