On 03/21/2016 01:34 PM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi,
>
> Working perfectly!
> Thanks for helping me remove this nasty workaround.
Thanks!
I sent the patch out and will pick it after standard review.
You can add a Tested-by tag on it if you want.
>> We should parse the OF n
Hi,
Working perfectly!
Thanks for helping me remove this nasty workaround.
> We should parse the OF node phy-mode, which describes which mode your
> PHY uses.
Right!
Best regards,
Denis Bakhvalov
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On 03/21/2016 09:16 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi,
Hi!
> I solved the Ethernet problem on our board.
>
> The problem was in the register below:
>
> Link:
> http://wl.altera.com/literature/hb/arria-v/hps.html#topic/sfo1410067853518.html
> Registers used by the EMACs. All
Hello Dear U-Boot support,
Please comment on this also.
I have custom board with Altera Arria 5 SocFpga onboard.
U-Boot version: 2016.03-rc1
I had probems with configuring fpga from u-boot:
U-Boot > bridge disable
U-Boot > run config_fpga
FPGA: Could not configure
Command failed, result=-2
So,
Hi,
I solved the Ethernet problem on our board.
The problem was in the register below:
Link:
http://wl.altera.com/literature/hb/arria-v/hps.html#topic/sfo1410067853518.html
Registers used by the EMACs. All fields are reset by a cold or warm reset.
Module Instance Base AddressRegister Addres
Hi,
> Why are you constantly hung on this FPGA part ? The ethernet is not
> routed through the FPGA, it is connected directly to the HPS. Thus,
> you don't have to care about the FPGA at all, you only care about the
> configuration of the HPS.
Please excuse me for my small experience in this topi
On 03/09/2016 06:25 PM, Marek Vasut wrote:
>
> Thanks for the test!
>
> The speed looks weird, it should be in the 2-3MiB range.
>
> Are you booting using mainline U-Boot SPL ? :-)
>
Yes, I'm using mainline SPL. This Arria5 board is really old so I can't
really say that I have good working H
On 03/10/2016 09:58 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi Marek, Dinh,
Hi,
>> Are you booting using mainline U-Boot SPL ? :-)
>
> No, we use SPL from U-Boot 2013.
> I can quess what you will say now, but it somehow worked before (combination
> SPL + U-Boot from 2013).
I will sa
Hi Marek, Dinh,
> Are you booting using mainline U-Boot SPL ? :-)
No, we use SPL from U-Boot 2013.
I can quess what you will say now, but it somehow worked before (combination
SPL + U-Boot from 2013).
Is there a way to capture fpga dumps?
I can then compare them to working case.
I can assume t
On 03/09/2016 10:40 PM, Dinh Nguyen wrote:
> On 03/09/2016 08:00 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
>> Hi Marek,
>>
>>> Perform usual test, disable cache (dcache off) .
>>
>> I tried and result is still the same.
>>
>> UPD: I did a little trick:
>> 1. I started ping from the board sid
On 03/09/2016 08:00 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi Marek,
>
>> Perform usual test, disable cache (dcache off) .
>
> I tried and result is still the same.
>
> UPD: I did a little trick:
> 1. I started ping from the board side. That made the board listen to incoming
> packe
Hi Marek,
> Perform usual test, disable cache (dcache off) .
I tried and result is still the same.
UPD: I did a little trick:
1. I started ping from the board side. That made the board listen to incoming
packets (calling in infinite loop eth_rx() ).
2. Started ping from PC side.
3. In this case
On 03/09/2016 10:22 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi,
>
>> However there is still no ping in U-Boot.
>> After power reset I did:
>>
>>> # bridge disable
>>> # fpga load 0
>>> # bridge enable
>>
>>> # md 0xff706000 1
>> ff706000: 0074 <-- this means fpga is in us
Hi,
> However there is still no ping in U-Boot.
> After power reset I did:
>
> ># bridge disable
> ># fpga load 0
> ># bridge enable
>
> ># md 0xff706000 1
> ff706000: 0074 <-- this means fpga is in user mode
>
> ># setenv ethaddr ...
> ># setenv ipaddr ...
> ># setenv netmask ...
>
Hi Marek,
> What do you mean by this ? Is your ethernet controller synthesised in
> the FPGA ? The arriaV socdk u-boot uses the top-side ethernet port,
> which is connected to the ethernet controller in the HPS.
I managed to get it working.
Right after configuring fpga from Linux I made a soft re
On 03/04/2016 01:53 PM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Hi,
Hi,
>> It seems like your PHY is not recongnised. Could there be some
>> reset line which is left asserted ?
>
> I'm afraid I don't know how to check that.
>
> But I have previous version of U-Boot (2013) where Ethernet
Hi,
> It seems like your PHY is not recongnised. Could there be some reset
> line which is left asserted ?
I'm afraid I don't know how to check that.
But I have previous version of U-Boot (2013) where Ethernet is working.
Maybe I can check it there?
I already tried to go that path, but code is q
On 03/04/2016 10:20 AM, Bakhvalov, Denis (Nokia - PL/Wroclaw) wrote:
> Dear U-Boot support,
>
> I'm migrating to new U-Boot version from 2013 and now have Ethernet
> not working both in U-Boot and in Linux (after booting).
>
> I have custom board with Altera Arria 5 SocFpga onboard. U-Boot
> vers
Dear U-Boot support,
I'm migrating to new U-Boot version from 2013 and now have Ethernet not working
both in U-Boot and in Linux (after booting).
I have custom board with Altera Arria 5 SocFpga onboard.
U-Boot version: 2016.03-rc1
In logs I can see:
Net: No ethernet found.
With more verbos
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