mple to output sample
> ratio, which can eventually lead to a lock up.
>
> Jonathon
>
> On Tue, Jan 29, 2019 at 3:11 AM Andrew Danowitz via USRP-users <
> usrp-users@lists.ettus.com> wrote:
>
>> I have an RFNOC block that, based on a control register can either
>
I have an RFNOC block that, based on a control register can either decimate
the signal it's working on or leave the output rate the same as the input
rate. If I set the control register to an initial value (either decimate,
or not decimate) and let the system run, it works fine in either mode. If I
>>
>>>> Hi Andrew,
>>>>
>>>> Have you tried using Chipscope to see where the issue is at in your
>>>> code? You want to look at the tvalid and tready AXI stream control signals
>>>> to pinpoint where your data flow stalls (i.e. tvali
Okay, I think I figured this one out. It seems like the queue structure
used to hold the payload for each packet wasn't getting properly
deleted/reinitialized between loop runs, so the queue got bigger with each
packet run until it became too big for xsim to handle leading to a freeze.
To fix, I ma
Hi all,
I'm trying to run a Vivado simulation to run 2mb of pre-recorded data
through an RFNOC IP block. I've modified the testbench created by
rfnocmodtool for this purpose. After sending about 5-10k data samples and
recording the results, the Vivado flow seems to ignore future testbench
commands
alid and tready AXI stream control signals
>>> to pinpoint where your data flow stalls (i.e. tvalid = 1 and tready = 0).
>>> Once you know where the stall is located, I can provide more advice.
>>>
>>> Jonathon
>>>
>>> On Wed, Dec 19, 2018 at 8:2
at the tvalid and tready AXI stream control signals to
> pinpoint where your data flow stalls (i.e. tvalid = 1 and tready = 0). Once
> you know where the stall is located, I can provide more advice.
>
> Jonathon
>
> On Wed, Dec 19, 2018 at 8:20 AM Andrew Danowitz via USRP-users &l
e axi_wrapper uses to
> create output packets when SIMPLE_MODE is disabled.
>
> Also, have you run in a simulation testbench? Simulation should be able to
> expose these issues before targetting hardware to make debugging a bit
> easier.
>
> EJ
>
>
>
> On Tue,
Hi all,
I'm trying to create an rfnoc block that takes in a stream of data at
Sample rate n, does some processing to turn i-q values into real samples,
and outputs data at a rate of n/2 by packing real values into both i and q
channels of the output stream. I've tried to incorporate the
axi_rate_c
Hi all,
We've been testing a design with a few RFNOC blocks, and after about a day
or two of running we're constantly getting timeout on channel 0 errors and
other signals. What's the best way to debug something like this? Is there a
way to figure out what block stops responding?
Thanks,
Andrew
Hi all,
I wrote some blocks in systemverilog that I'd like to use in an rfnoc block
I have. When I add max_find.sv to the Makefile.srcs, the build tools claim
they can't find my max_find module. If I save it as max_find.v, the build
tools can find the file, but it gets treated as standard Verilog.
Make sure you don't have a version of gnuradio installed through your
repository manager. Sometimes gnuradio will grab the wrong header files if
there are multiple versions installed.
On Tue, Sep 11, 2018 at 10:06 AM, Rob Kossler via USRP-users <
usrp-users@lists.ettus.com> wrote:
> Hi,
> I just
I've never gotten this error on a cross-compile build, but I have gotten it
on an rfnoc build. In my case, the linker was finding headers from a system
install of gnuradio and trying to use those instead of the fresh ones
generated by make. I might uninstall any repository installs of gnuradio or
t
Forgot to reply all, but see below:
On Wed, Sep 5, 2018 at 12:57 PM, Andrew Danowitz wrote:
> I've worked around this by:
> 1) going into the prefix directory
> 2) source environment-setup-armv7ahf-vfp-neon-oe-linux-gnueabi (this sets
> your environment to use the built in python)
> 3) download
It's true that uhd_image_builder.py will pull in all RFNOC IPs
automatically, but if you go to simulate an OOT rfnoc block that relies on
an IP, in my experience, you have to launch Vivado and add the UHD IP
directory to your project.
On Mon, Sep 3, 2018 at 8:43 PM, Jon Pendlum via USRP-users <
us
When I try to use axi_round_and_clip in my design, simulation won't run and
has weird internal simulation issues. If I build it into an rfnoc image,
the flow graph doesn't return any data. Has anyone else run into this?
--
Information contained, linked, or attached to this email and all verbal
Hi Brent,
Sounds good. I think the gnuradio pybombs recipe pulls in volk as a
submodule. I think they manage it with the line "gitargs: --recursive" in
their recipe.
On Fri, Aug 31, 2018 at 2:15 PM, Brent Stapleton via USRP-users <
usrp-users@lists.ettus.com> wrote:
> The underlying reason for t
I used rfnocmodtool from UHD3.13 to generate a new noc block. The id it
assigned the block had a leading 0. Unfortunately, the tool appears to have
dropped the leading 0 in the auto-generated xml file, which led to grc and
uhd_usrp_probe not being able to find the controller and name for the block.
As a note, these mismatches can occur if you use pybombs to manage your
install and do pybombs update uhd-fpga. If you're a pybombs user, my
recommendation is to ignore the uhd-fpga directory altogether, and from
within uhd/fpga run git submodule init, followed by git pull.
Brent, is this somethin
he values (which is the point of it).
>
>
>
> - Original Message -
> Subject: [USRP-users] Multiple instances of RFNOC block in single flow
> graph
> From: "Andrew Danowitz via USRP-users"
> Date: 8/28/18 5:34 pm
> To: "shachar J. brown via USRP-users"
Hi all,
Has anyone used multiple instances of an RFNOC block in a single flow
graph? I Built an image with my block, mAvgFilter, twice in the build args.
When I try to use both in a flow graph, though, I get:
File "/home/root/e300/src/test_code/top_block.py", line 255, in __init__
self.device
Hi all,
I'm trying to create an rfnoc divide block. I have the RTL and testbench
set up and working, but every time I try to put it in a grc flow, I get:
RuntimeError: Invalid stream args.
I'm assuming this has to do with the grc xml file for my block. Is there
any documentation on how to make a
Update, I get this error even if I don't use any rfnoc components, and just
use a standard UHD source going into the qt gui time sink.
Thanks,
Andrew
On Wed, Aug 22, 2018 at 11:12 AM, Andrew Danowitz <
and...@whitefoxdefense.com> wrote:
> Hi,
>
> I rebuilt everything using the latest recipes for
Hi,
I rebuilt everything using the latest recipes for rfnoc and e3xx-rfnoc. Now
when I try to run any rfnoc flow-chart on the e310, I get the following
error:
ValueError: recv_buff_size must be larger than the recv_frame_size.
Even if I just take an rfnoc: radio block and connect it directly to
When you source environment-setup-armv7ahf-vfp-neon-oe-linux-gnueabi it
points python to the e310/ARM version of Python that comes to the SDK.
Since gr_modtool needs to run on your host system to set up a new OOT
module, the ARM version of python won't work for you. Your best bet is to
open a new t
Hi,
I generated an rfnoc fpga image using the latest UHD-fpga tools on the
rfnoc-devel branch. When I go to run it with the latest UHD on the
rfnoc-devel branch, I get RuntimeError: RuntimeError: FPGA component
`noc_shell' is revision 4 and UHD supports revision 2. Please either
upgrade UHD (reco
I recently upgraded to the newest versions of the development tools (fresh
pybombs installs of recipes rfnoc-e3xx for cross-compiling, and rfnoc for
local test and development). Since that time, all of my previously
functioning custom RFNOC blocks now hang in simulation on Vivado (they hang
at the
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