Am Dienstag, 10. August 2010 15:23:30 schrieb Marc Kleine-Budde: > Heinz-Jürgen Oertel wrote: > > Hello, > > can please someone confirm that the more stable crystal oscillator > > frequency can be used to drive the FlexCAN module instead of the 66.5 MHz > > PLL clock? > > According to the datasheet the CLK_SRC Bit of the CTRL reg selects the > CAN engine clock. I don't know which clock is more stable.
From the manual:
13 This bit selects the clock source to the CAN protocol interface
(CPI) to be either the peripheral clock (driven by CLK_SRC
the PLL) or the crystal oscillator clock.
The selected clock is the one fed to the prescaler to generate
the SCLK (SCLK). In order to guarantee reliable operation,
this bit must only be changed while the module is in disable
mode. See Section 24.4.8.4, "Protocol Timing," for more information.
0 The CAN engine clock source is the oscillator clock (24.576 MHz)
1 The CAN engine clock source is the bus clock (66.5 MHz)
and in "24.4.8.4 Protocol Timing"
The crystal oscillator clock must be selected
whenever a tight tolerance (up to 0.1%) is required in the CAN bus timing.
The crystal oscillator clock has better jitter performance
than PLL-generated clocks.
especially with 1 Mbit/s it's better to use the crystal oscillator clock.
> However the mainline driver only supports the bus clock.
and with this clock, if it is 66.5 MHz, one Mbit/s can not be reached.
> Patches are, as
> always, welcome.
Once I know how to do it, than let's see.
For now it's really difficult to dive into such system internals.
It's difficult to read the hardware manual describing the clocks and even more
difficult to find and _use_ the already available BSP functions and consider
all side effects. That is may problem. Only setting bit 13 in the clock
control register seems not to be the solution. Doing it, my system freezes
completely (kernel 2.6.32.)
>
> cheers, Marc
>
Heinz
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