Module Name: src
Committed By: skrll
Date: Mon Jul 23 15:51:48 UTC 2012
Modified Files:
src/sys/arch/arm/arm: cpufunc.c
src/sys/arch/arm/include: armreg.h
Log Message:
Make auxiliary register naming consistent for the 1136.
To generate a diff of this commit:
cvs rdiff -u -r1.108 -r1.109 src/sys/arch/arm/arm/cpufunc.c
cvs rdiff -u -r1.55 -r1.56 src/sys/arch/arm/include/armreg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc.c
diff -u src/sys/arch/arm/arm/cpufunc.c:1.108 src/sys/arch/arm/arm/cpufunc.c:1.109
--- src/sys/arch/arm/arm/cpufunc.c:1.108 Sat Jul 21 12:19:15 2012
+++ src/sys/arch/arm/arm/cpufunc.c Mon Jul 23 15:51:48 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: cpufunc.c,v 1.108 2012/07/21 12:19:15 skrll Exp $ */
+/* $NetBSD: cpufunc.c,v 1.109 2012/07/23 15:51:48 skrll Exp $ */
/*
* arm7tdmi support code Copyright (c) 2001 John Fremlin
@@ -49,7 +49,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.108 2012/07/21 12:19:15 skrll Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpufunc.c,v 1.109 2012/07/23 15:51:48 skrll Exp $");
#include "opt_compat_netbsd.h"
#include "opt_cpuoptions.h"
@@ -2993,8 +2993,8 @@ arm11x6_setup(char *args)
*/
if ((cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM1136JS) { /* ARM1136JSr0pX */
cpuctrl |= CPU_CONTROL_FI_ENABLE;
- auxctrl = ARM11R0_AUXCTL_PFI;
- auxctrl_wax = ~ARM11R0_AUXCTL_PFI;
+ auxctrl = ARM1136_AUXCTL_PFI;
+ auxctrl_wax = ~ARM1136_AUXCTL_PFI;
}
/*
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.55 src/sys/arch/arm/include/armreg.h:1.56
--- src/sys/arch/arm/include/armreg.h:1.55 Tue Jul 17 06:12:11 2012
+++ src/sys/arch/arm/include/armreg.h Mon Jul 23 15:51:48 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.55 2012/07/17 06:12:11 skrll Exp $ */
+/* $NetBSD: armreg.h,v 1.56 2012/07/23 15:51:48 skrll Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -317,13 +317,6 @@
#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
-/* ARM11r0 Auxiliary Control Register (CP15 register 1, opcode2 1) */
-#define ARM11R0_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */
- /* This is an undocumented flag
- * used to work around a cache bug
- * in r0 steppings. See errata
- * 364296.
- */
/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */
#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */
@@ -334,6 +327,13 @@
#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */
#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */
+/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */
+#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */
+ /* This is an undocumented flag
+ * used to work around a cache bug
+ * in r0 steppings. See errata
+ * 364296.
+ */
/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */
#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */
