Module Name: src
Committed By: matt
Date: Wed Aug 29 17:44:25 UTC 2012
Modified Files:
src/sys/arch/arm/arm32: cpu.c
src/sys/arch/arm/include: armreg.h cpu.h
src/sys/arch/arm/mainbus: cpu_mainbus.c
Log Message:
Use new armv7 CP15 register to print out cache types.
If the cpu_cc_freq is set, report it.
Add macros to make inlines for reading/writing co-processor registers.
To generate a diff of this commit:
cvs rdiff -u -r1.84 -r1.85 src/sys/arch/arm/arm32/cpu.c
cvs rdiff -u -r1.59 -r1.60 src/sys/arch/arm/include/armreg.h
cvs rdiff -u -r1.69 -r1.70 src/sys/arch/arm/include/cpu.h
cvs rdiff -u -r1.11 -r1.12 src/sys/arch/arm/mainbus/cpu_mainbus.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm32/cpu.c
diff -u src/sys/arch/arm/arm32/cpu.c:1.84 src/sys/arch/arm/arm32/cpu.c:1.85
--- src/sys/arch/arm/arm32/cpu.c:1.84 Tue Aug 14 20:39:49 2012
+++ src/sys/arch/arm/arm32/cpu.c Wed Aug 29 17:44:25 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu.c,v 1.84 2012/08/14 20:39:49 matt Exp $ */
+/* $NetBSD: cpu.c,v 1.85 2012/08/29 17:44:25 matt Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -46,15 +46,16 @@
#include <sys/param.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.84 2012/08/14 20:39:49 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.85 2012/08/29 17:44:25 matt Exp $");
#include <sys/systm.h>
-#include <sys/malloc.h>
+#include <sys/conf.h>
+#include <sys/cpu.h>
#include <sys/device.h>
+#include <sys/kmem.h>
#include <sys/proc.h>
-#include <sys/conf.h>
+
#include <uvm/uvm_extern.h>
-#include <machine/cpu.h>
#include <arm/cpuconf.h>
#include <arm/undefined.h>
@@ -66,45 +67,94 @@ __KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.84
char cpu_model[256];
+#ifdef MULTIPROCESSOR
+volatile u_int arm_cpu_hatched = 0;
+u_int arm_cpu_max = 0;
+uint32_t arm_cpu_mbox __cacheline_aligned = 0;
+uint32_t arm_cpu_marker __cacheline_aligned = 1;
+#endif
+
/* Prototypes */
void identify_arm_cpu(device_t dv, struct cpu_info *);
+void identify_cortex_caches(device_t dv);
+void identify_features(device_t dv);
/*
* Identify the master (boot) CPU
*/
void
-cpu_attach(device_t dv)
+cpu_attach(device_t dv, cpuid_t id)
{
- int usearmfpe;
+ struct cpu_info *ci;
+
+ if (id == 0) {
+ ci = curcpu();
- usearmfpe = 1; /* when compiled in, its enabled by default */
+ /* Get the CPU ID from coprocessor 15 */
+
+ ci->ci_arm_cpuid = cpu_id();
+ ci->ci_arm_cputype = ci->ci_arm_cpuid & CPU_ID_CPU_MASK;
+ ci->ci_arm_cpurev = ci->ci_arm_cpuid & CPU_ID_REVISION_MASK;
+ } else {
+#ifdef MULTIPROCESSOR
+ KASSERT(cpu_info[id] == NULL);
+ ci = kmem_zalloc(sizeof(*ci), KM_SLEEP);
+ KASSERT(ci != NULL);
+ ci->ci_cpl = IPL_HIGH;
+ ci->ci_cpuid = id;
+ ci->ci_data.cpu_core_id = id;
+ ci->ci_data.cpu_cc_freq = cpu_info_store.ci_data.cpu_cc_freq;
+ ci->ci_arm_cpuid = cpu_info_store.ci_arm_cpuid;
+ ci->ci_arm_cputype = cpu_info_store.ci_arm_cputype;
+ ci->ci_arm_cpurev = cpu_info_store.ci_arm_cpurev;
+ cpu_info[ci->ci_cpuid] = ci;
+ if ((arm_cpu_hatched & (1 << id)) == 0) {
+ ci->ci_dev = dv;
+ dv->dv_private = ci;
+ aprint_naive(": disabled\n");
+ aprint_normal(": disabled (unresponsive)\n");
+ return;
+ }
+#else
+ aprint_naive(": disabled\n");
+ aprint_normal(": disabled (uniprocessor kernel)\n");
+ return;
+#endif
+ }
- curcpu()->ci_dev = dv;
+ ci->ci_dev = dv;
+ dv->dv_private = ci;
- evcnt_attach_dynamic(&curcpu()->ci_arm700bugcount, EVCNT_TYPE_MISC,
- NULL, dv->dv_xname, "arm700swibug");
-
- /* Get the CPU ID from coprocessor 15 */
+ evcnt_attach_dynamic(&ci->ci_arm700bugcount, EVCNT_TYPE_MISC,
+ NULL, device_xname(dv), "arm700swibug");
- curcpu()->ci_arm_cpuid = cpu_id();
- curcpu()->ci_arm_cputype = curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK;
- curcpu()->ci_arm_cpurev =
- curcpu()->ci_arm_cpuid & CPU_ID_REVISION_MASK;
+#ifdef MULTIPROCESSOR
+ /*
+ * and we are done if this is a secondary processor.
+ */
+ if (!CPU_IS_PRIMARY(ci)) {
+ aprint_naive(": %s\n", cpu_model);
+ aprint_normal(": %s\n", cpu_model);
+ mi_cpu_attach(ci);
+ return;
+ }
+#endif
- identify_arm_cpu(dv, curcpu());
+ identify_arm_cpu(dv, ci);
- if (curcpu()->ci_arm_cputype == CPU_ID_SA110 &&
- curcpu()->ci_arm_cpurev < 3) {
- aprint_normal("%s: SA-110 with bugged STM^ instruction\n",
- dv->dv_xname);
+#ifdef CPU_STRONGARM
+ if (ci->ci_arm_cputype == CPU_ID_SA110 &&
+ ci->ci_arm_cpurev < 3) {
+ aprint_normal_dev(dv, "SA-110 with bugged STM^ instruction\n");
}
+#endif
#ifdef CPU_ARM8
- if ((curcpu()->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) {
+ if ((ci->ci_arm_cpuid & CPU_ID_CPU_MASK) == CPU_ID_ARM810) {
int clock = arm8_clock_config(0, 0);
char *fclk;
- aprint_normal("%s: ARM810 cp15=%02x", dv->dv_xname, clock);
+ aprint_normal_dev(dv, "ARM810 cp15=%02x", clock);
aprint_normal(" clock:%s", (clock & 1) ? " dynamic" : "");
aprint_normal("%s", (clock & 2) ? " sync" : "");
switch ((clock >> 2) & 3) {
@@ -150,6 +200,7 @@ cpu_attach(device_t dv)
*/
+ int usearmfpe = 1;
if (boot_args)
get_bootconf_option(boot_args, "armfpe",
BOOTOPT_TYPE_BOOLEAN, &usearmfpe);
@@ -493,12 +544,11 @@ static const char * const wtnames[] = {
void
identify_arm_cpu(device_t dv, struct cpu_info *ci)
{
- u_int cpuid;
enum cpu_class cpu_class = CPU_CLASS_NONE;
- int i;
+ const u_int cpuid = ci->ci_arm_cpuid;
+ const char * const xname = device_xname(dv);
const char *steppingstr;
-
- cpuid = ci->ci_arm_cpuid;
+ int i;
if (cpuid == 0) {
aprint_error("Processor failed probe - no CPU ID\n");
@@ -521,10 +571,19 @@ identify_arm_cpu(device_t dv, struct cpu
if (cpuids[i].cpuid == 0)
sprintf(cpu_model, "unknown CPU (ID = 0x%x)", cpuid);
- aprint_naive(": %s\n", cpu_model);
- aprint_normal(": %s\n", cpu_model);
+ if (ci->ci_data.cpu_cc_freq != 0) {
+ char freqbuf[8];
+ humanize_number(freqbuf, sizeof(freqbuf), ci->ci_data.cpu_cc_freq,
+ "Hz", 1000);
+
+ aprint_naive(": %s %s\n", freqbuf, cpu_model);
+ aprint_normal(": %s %s\n", freqbuf, cpu_model);
+ } else {
+ aprint_naive(": %s\n", cpu_model);
+ aprint_normal(": %s\n", cpu_model);
+ }
- aprint_normal("%s:", dv->dv_xname);
+ aprint_normal("%s:", xname);
switch (cpu_class) {
case CPU_CLASS_ARM6:
@@ -573,26 +632,33 @@ identify_arm_cpu(device_t dv, struct cpu
aprint_normal("\n");
+#ifdef CPU_CORTEX
+ if (CPU_ID_CORTEX_P(cpuid)) {
+ identify_cortex_caches(dv);
+ if (0)
+ identify_features(dv);
+ } else
+#endif
/* Print cache info. */
- if (arm_picache_line_size == 0 && arm_pdcache_line_size == 0)
- goto skip_pcache;
+ if (arm_picache_line_size != 0 || arm_pdcache_line_size != 0) {
+
+ if (arm_pcache_unified) {
+ aprint_normal_dev(dv, "%dKB/%dB %d-way %s unified cache\n",
+ arm_pdcache_size / 1024,
+ arm_pdcache_line_size, arm_pdcache_ways,
+ wtnames[arm_pcache_type]);
+ } else {
+ aprint_normal_dev(dv, "%dKB/%dB %d-way Instruction cache\n",
+ arm_picache_size / 1024,
+ arm_picache_line_size, arm_picache_ways);
+ aprint_normal_dev(dv, "%dKB/%dB %d-way %s Data cache\n",
+ arm_pdcache_size / 1024,
+ arm_pdcache_line_size, arm_pdcache_ways,
+ wtnames[arm_pcache_type]);
+ }
- if (arm_pcache_unified) {
- aprint_normal("%s: %dKB/%dB %d-way %s unified cache\n",
- dv->dv_xname, arm_pdcache_size / 1024,
- arm_pdcache_line_size, arm_pdcache_ways,
- wtnames[arm_pcache_type]);
- } else {
- aprint_normal("%s: %dKB/%dB %d-way Instruction cache\n",
- dv->dv_xname, arm_picache_size / 1024,
- arm_picache_line_size, arm_picache_ways);
- aprint_normal("%s: %dKB/%dB %d-way %s Data cache\n",
- dv->dv_xname, arm_pdcache_size / 1024,
- arm_pdcache_line_size, arm_pdcache_ways,
- wtnames[arm_pcache_type]);
}
- skip_pcache:
switch (cpu_class) {
#ifdef CPU_ARM2
@@ -646,19 +712,100 @@ identify_arm_cpu(device_t dv, struct cpu
#endif
break;
default:
- if (cpu_classes[cpu_class].class_option == NULL)
- aprint_error("%s: %s does not fully support this CPU."
- "\n", dv->dv_xname, ostype);
- else {
- aprint_error("%s: This kernel does not fully support "
- "this CPU.\n", dv->dv_xname);
- aprint_normal("%s: Recompile with \"options %s\" to "
- "correct this.\n", dv->dv_xname,
- cpu_classes[cpu_class].class_option);
+ if (cpu_classes[cpu_class].class_option == NULL) {
+ aprint_error_dev(dv, "%s does not fully support this CPU.\n",
+ ostype);
+ } else {
+ aprint_error_dev(dv, "This kernel does not fully support "
+ "this CPU.\n");
+ aprint_normal_dev(dv, "Recompile with \"options %s\" to "
+ "correct this.\n", cpu_classes[cpu_class].class_option);
}
break;
}
-
}
-/* End of cpu.c */
+#ifdef CPU_CORTEX
+static void
+print_cortex_cache(device_t dv, u_int level, const char *desc)
+{
+ uint32_t ccsidr = armreg_ccsidr_read();
+ u_int linesize = 1 << ((ccsidr & 7) + 4);
+ u_int nways = ((ccsidr >> 3) & 0x3ff) + 1;
+ u_int nsets = ((ccsidr >> 13) & 0x7fff) + 1;
+ u_int totalsize = linesize * nways * nsets;
+ static const char * const wstrings[] = {
+ "", " write-back", " write-through", ""
+ };
+ static const char * const astrings[] = {
+ "",
+ " with write allocate",
+ " with read allocate",
+ " with read and write allocate"
+ };
+
+ //aprint_debug_dev(dv, "ccsidr=%#x\n", ccsidr);
+
+ u_int wtype = (ccsidr >> 30) & 3;
+ u_int atype = (ccsidr >> 28) & 3;
+
+ aprint_normal_dev(dv, "%uKB/%uB %u-way%s L%u %s cache%s\n",
+ totalsize / 1024, linesize, nways, wstrings[wtype], level + 1,
+ desc, astrings[atype]);
+}
+
+void
+identify_cortex_caches(device_t dv)
+{
+ const uint32_t orig_csselr = armreg_csselr_read();
+ uint32_t clidr = armreg_clidr_read();
+ u_int level;
+
+ //aprint_debug_dev(dv, "clidr=%011o\n", clidr);
+
+ for (level = 0, clidr &= 077777777; clidr & 7; clidr >>= 3, level++) {
+ if (clidr & 1) {
+ armreg_csselr_write(2*level + 1);
+ print_cortex_cache(dv, level, "Instruction");
+ }
+ if (clidr & 6) {
+ armreg_csselr_write(2*level + 0);
+ print_cortex_cache(dv, level,
+ (clidr & 4) ? "Unified" : "Data");
+ }
+ }
+
+ armreg_csselr_write(orig_csselr);
+
+
+}
+
+void
+identify_features(device_t dv)
+{
+ uint32_t isar0 = armreg_isar0_read();
+ uint32_t isar1 = armreg_isar1_read();
+ uint32_t isar2 = armreg_isar2_read();
+ uint32_t isar3 = armreg_isar3_read();
+ uint32_t isar4 = armreg_isar4_read();
+ uint32_t isar5 = armreg_isar5_read();
+
+ uint32_t mmfr0 = armreg_mmfr0_read();
+ uint32_t mmfr1 = armreg_mmfr1_read();
+ uint32_t mmfr2 = armreg_mmfr2_read();
+ uint32_t mmfr3 = armreg_mmfr3_read();
+
+ uint32_t pfr0 = armreg_pfr0_read();
+ uint32_t pfr1 = armreg_pfr1_read();
+
+ aprint_normal_dev(dv,
+ "isar: [0]=%#x [1]=%#x [2]=%#x [3]=%#x, [4]=%#x, [5]=%#x\n",
+ isar0, isar1, isar2, isar3, isar4, isar5);
+ aprint_normal_dev(dv,
+ "mmfr: [0]=%#x [1]=%#x [2]=%#x [3]=%#x\n",
+ mmfr0, mmfr1, mmfr2, mmfr3);
+ aprint_normal_dev(dv,
+ "pfr: [0]=%#x [1]=%#x\n",
+ pfr0, pfr1);
+}
+#endif /* CPU_CORTEX */
Index: src/sys/arch/arm/include/armreg.h
diff -u src/sys/arch/arm/include/armreg.h:1.59 src/sys/arch/arm/include/armreg.h:1.60
--- src/sys/arch/arm/include/armreg.h:1.59 Wed Aug 15 17:20:27 2012
+++ src/sys/arch/arm/include/armreg.h Wed Aug 29 17:44:25 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: armreg.h,v 1.59 2012/08/15 17:20:27 matt Exp $ */
+/* $NetBSD: armreg.h,v 1.60 2012/08/29 17:44:25 matt Exp $ */
/*
* Copyright (c) 1998, 2001 Ben Harris
@@ -212,8 +212,9 @@
#define CPU_ID_CORTEXA9R4 0x413fc090
#define CPU_ID_CORTEXA15R2 0x412fc0f0
#define CPU_ID_CORTEXA15R3 0x413fc0f0
-#define CPU_ID_CORTEX_P(n) ((n & 0xff0fff00) == 0x410fc000)
-#define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ffff0) == 0x410fc080)
+#define CPU_ID_CORTEX_P(n) ((n & 0xff0ff000) == 0x410fc000)
+#define CPU_ID_CORTEX_A8_P(n) ((n & 0xff0ff0f0) == 0x410fc080)
+#define CPU_ID_CORTEX_A9_P(n) ((n & 0xff0ff0f0) == 0x410fc090)
#define CPU_ID_SA110 0x4401a100
#define CPU_ID_SA1100 0x4401a110
#define CPU_ID_TI925T 0x54029250
@@ -343,6 +344,16 @@
#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */
#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */
+/* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode2 1) */
+#define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Enable parity */
+#define CORTEXA9_AUXCTL_1WAY 0x00000100 /* Alloc in one way only */
+#define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache */
+#define CORTEXA9_AUXCTL_SMP 0x00000040 /* CPU is in SMP mode */
+#define CORTEXA9_AUXCTL_WRZERO 0x00000008 /* Write full line of zeroes */
+#define CORTEXA9_AUXCTL_L1PLD 0x00000004 /* L1 Dside prefetch */
+#define CORTEXA9_AUXCTL_L2PLD 0x00000002 /* L2 Dside prefetch */
+#define CORTEXA9_AUXCTL_FW 0x00000001 /* Forward Cache/TLB ops */
+
/* XScale Auxiliary Control Register (CP15 register 1, opcode2 1) */
#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */
#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */
@@ -359,6 +370,16 @@
#define MPCORE_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */
#define MPCORE_AUXCTL_SA 0x00000020 /* SMP/AMP */
+/* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */
+#define CORTEXA9_AUXCTL_FW 0x00000001 /* Cache and TLB updates broadcast */
+#define CORTEXA9_AUXCTL_L2_PLD 0x00000002 /* Prefetch hint enable */
+#define CORTEXA9_AUXCTL_L1_PLD 0x00000004 /* Data prefetch hint enable */
+#define CORTEXA9_AUXCTL_WR_ZERO 0x00000008 /* Ena. write full line of 0s mode */
+#define CORTEXA9_AUXCTL_SMP 0x00000040 /* Coherency is active */
+#define CORTEXA9_AUXCTL_EXCL 0x00000080 /* Exclusive cache bit */
+#define CORTEXA9_AUXCTL_ONEWAY 0x00000100 /* Allocate in on cache way only */
+#define CORTEXA9_AUXCTL_PARITY 0x00000200 /* Support parity checking */
+
/* Marvell Feroceon Extra Features Register (CP15 register 1, opcode2 0) */
#define FC_DCACHE_REPL_LOCK 0x80000000 /* Replace DCache Lock */
#define FC_DCACHE_STREAM_EN 0x20000000 /* DCache Streaming Switch */
@@ -509,4 +530,72 @@
#define CORTEX_CNTENC_C __BIT(31) /* Disables the cycle counter */
#define CORTEX_CNTOFL_C __BIT(31) /* Cycle counter overflow flag */
+#ifndef _LOCORE
+#define ARMREG_READ_INLINE(name, __insnstring) \
+static inline uint32_t armreg_##name##_read(void) \
+{ \
+ uint32_t __rv; \
+ __asm __volatile("mrc " __insnstring : "=r"(__rv)); \
+ return __rv; \
+}
+
+#define ARMREG_WRITE_INLINE(name, __insnstring) \
+static inline void armreg_##name##_write(uint32_t __val) \
+{ \
+ __asm __volatile("mcr " __insnstring :: "r"(__val)); \
+}
+
+/* c0 registers */
+ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */
+ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */
+ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */
+ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */
+ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */
+ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */
+ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */
+ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */
+ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */
+ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */
+ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */
+ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */
+ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */
+ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */
+ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */
+ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */
+ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */
+ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
+ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */
+/* c2 registers */
+ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
+ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */
+/* c9 registers */
+ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
+ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */
+ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */
+ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */
+ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */
+ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */
+ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */
+ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */
+ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
+ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */
+/* c13 registers */
+ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
+ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */
+ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */
+/* c13 registers */
+ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */
+ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */
+ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */
+ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */
+
+
+#define MPIDR_31 0x80000000
+#define MPIDR_U 0x40000000 // 1 = Uniprocessor
+#define MPIDR_MT 0x01000000 // AFF0 for SMT
+#define MPIDR_AFF2 0x00ff0000
+#define MPIDR_AFF1 0x0000ff00
+#define MPIDR_AFF0 0x000000ff
+
+#endif /* _LOCORE*/
#endif /* _ARM_ARMREG_H */
Index: src/sys/arch/arm/include/cpu.h
diff -u src/sys/arch/arm/include/cpu.h:1.69 src/sys/arch/arm/include/cpu.h:1.70
--- src/sys/arch/arm/include/cpu.h:1.69 Wed Aug 29 07:14:05 2012
+++ src/sys/arch/arm/include/cpu.h Wed Aug 29 17:44:25 2012
@@ -352,7 +352,7 @@ void cpu_proc_fork(struct proc *, struct
*/
struct device;
-void cpu_attach(struct device *);
+void cpu_attach(device_t, cpuid_t);
#endif
/*
Index: src/sys/arch/arm/mainbus/cpu_mainbus.c
diff -u src/sys/arch/arm/mainbus/cpu_mainbus.c:1.11 src/sys/arch/arm/mainbus/cpu_mainbus.c:1.12
--- src/sys/arch/arm/mainbus/cpu_mainbus.c:1.11 Sun Jun 5 17:03:16 2011
+++ src/sys/arch/arm/mainbus/cpu_mainbus.c Wed Aug 29 17:44:25 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: cpu_mainbus.c,v 1.11 2011/06/05 17:03:16 matt Exp $ */
+/* $NetBSD: cpu_mainbus.c,v 1.12 2012/08/29 17:44:25 matt Exp $ */
/*
* Copyright (c) 1995 Mark Brinicombe.
@@ -42,7 +42,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: cpu_mainbus.c,v 1.11 2011/06/05 17:03:16 matt Exp $");
+__KERNEL_RCSID(0, "$NetBSD: cpu_mainbus.c,v 1.12 2012/08/29 17:44:25 matt Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -88,7 +88,7 @@ cpu_mainbus_match(device_t parent, cfdat
static void
cpu_mainbus_attach(device_t parent, device_t self, void *aux)
{
- cpu_attach(self);
+ cpu_attach(self, 0);
}
CFATTACH_DECL_NEW(cpu_mainbus, 0,
