Module Name: src
Committed By: matt
Date: Thu Sep 6 02:07:25 UTC 2012
Modified Files:
src/sys/arch/arm/arm: cpufunc_asm_armv7.S
src/sys/arch/arm/include/arm32: pmap.h
Log Message:
Enable "shareable" access to the page table for armv7. PTE_SYNC only does
a DSB now on an armv7 cpu and no longer needs to flush the cache line to ram.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/arm/cpufunc_asm_armv7.S
cvs rdiff -u -r1.107 -r1.108 src/sys/arch/arm/include/arm32/pmap.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/arm/cpufunc_asm_armv7.S
diff -u src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.3 src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.4
--- src/sys/arch/arm/arm/cpufunc_asm_armv7.S:1.3 Wed Aug 29 18:37:14 2012
+++ src/sys/arch/arm/arm/cpufunc_asm_armv7.S Thu Sep 6 02:07:25 2012
@@ -71,6 +71,10 @@ END(armv7_tlb_flushID_SE)
ENTRY(armv7_setttb)
+ mrc p15, 0, r1, c0, c0, 5 @ get MPIDR
+ cmp r1, #0
+ orrlt r0, #0x5b @ MP, cachable (Normal in/out WB)
+ orrge r0, #0x1b @ Non-MP, cacheable, normal WB
mcr p15, 0, r0, c2, c0, 0 @ load new TTB
#ifdef MULTIPROCESSOR
mcr p15, 0, r0, c8, c3, 0 @ invalidate all I+D TLBs
Index: src/sys/arch/arm/include/arm32/pmap.h
diff -u src/sys/arch/arm/include/arm32/pmap.h:1.107 src/sys/arch/arm/include/arm32/pmap.h:1.108
--- src/sys/arch/arm/include/arm32/pmap.h:1.107 Sun Sep 2 14:43:21 2012
+++ src/sys/arch/arm/include/arm32/pmap.h Thu Sep 6 02:07:25 2012
@@ -1,4 +1,4 @@
-/* $NetBSD: pmap.h,v 1.107 2012/09/02 14:43:21 matt Exp $ */
+/* $NetBSD: pmap.h,v 1.108 2012/09/06 02:07:25 matt Exp $ */
/*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
@@ -405,7 +405,7 @@ extern int pmap_needs_pte_sync;
#if (ARM_MMU_SA1 + ARM_MMU_V6 + ARM_MMU_V7 != 0) && (ARM_NMMUS == 1)
#define PMAP_INCLUDE_PTE_SYNC
#if (ARM_MMU_V7 > 0)
-#define PMAP_NEEDS_PTE_SYNC 1
+#define PMAP_NEEDS_PTE_SYNC 0
#else
#define PMAP_NEEDS_PTE_SYNC 1
#endif
