Module Name: src
Committed By: jmcneill
Date: Fri Dec 26 16:53:33 UTC 2014
Added Files:
src/sys/arch/arm/rockchip: files.rockchip obio.c obio_com.c
rockchip_dma.c rockchip_dwctwo.c rockchip_intr.h rockchip_reg.h
rockchip_space.c rockchip_var.h
src/sys/arch/evbarm/conf: ROCKCHIP files.rockchip mk.rockchip
std.rockchip
src/sys/arch/evbarm/rockchip: genassym.cf platform.h rockchip_machdep.c
rockchip_start.S
Log Message:
Initial support for Rockchip RK3066 / RK3188 SoCs, from Hiroshi Tokuda
<[email protected]> on port-arm:
http://mail-index.netbsd.org/port-arm/2014/10/09/msg002651.html
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/rockchip/files.rockchip \
src/sys/arch/arm/rockchip/obio.c src/sys/arch/arm/rockchip/obio_com.c \
src/sys/arch/arm/rockchip/rockchip_dma.c \
src/sys/arch/arm/rockchip/rockchip_dwctwo.c \
src/sys/arch/arm/rockchip/rockchip_intr.h \
src/sys/arch/arm/rockchip/rockchip_reg.h \
src/sys/arch/arm/rockchip/rockchip_space.c \
src/sys/arch/arm/rockchip/rockchip_var.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbarm/conf/ROCKCHIP \
src/sys/arch/evbarm/conf/files.rockchip \
src/sys/arch/evbarm/conf/mk.rockchip \
src/sys/arch/evbarm/conf/std.rockchip
cvs rdiff -u -r0 -r1.1 src/sys/arch/evbarm/rockchip/genassym.cf \
src/sys/arch/evbarm/rockchip/platform.h \
src/sys/arch/evbarm/rockchip/rockchip_machdep.c \
src/sys/arch/evbarm/rockchip/rockchip_start.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/arm/rockchip/files.rockchip
diff -u /dev/null src/sys/arch/arm/rockchip/files.rockchip:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/files.rockchip Fri Dec 26 16:53:33 2014
@@ -0,0 +1,42 @@
+# $NetBSD: files.rockchip,v 1.1 2014/12/26 16:53:33 jmcneill Exp $
+#
+# Configuration info for Rockchip ARM Peripherals
+#
+
+include "arch/arm/pic/files.pic"
+include "arch/arm/cortex/files.cortex"
+
+file arch/arm/arm32/arm32_boot.c
+file arch/arm/arm32/arm32_kvminit.c
+file arch/arm/arm32/arm32_reboot.c
+file arch/arm/arm32/irq_dispatch.S
+
+file arch/arm/rockchip/rockchip_space.c obio
+#file arch/arm/rockchip/rockchip_a4x_space.c obio
+file arch/arm/rockchip/rockchip_dma.c
+file arch/arm/arm/bus_space_a4x.S obio
+
+# On-board I/O
+device obio {[addr = -1], [size = -1], [width = -1], [intr = -1], [mult = 1]}: bus_space_generic
+attach obio at mainbus
+file arch/arm/rockchip/obio.c obio
+
+# serial
+attach com at obio with obiouart
+file arch/arm/rockchip/obio_com.c obiouart
+
+# SDHC
+#attach sdhc at obio with rksdhc
+#file arch/arm/rockchip/rockchip_sdhc.c rksdhc
+
+# USB OTG (Synopsys DesignWave OTG)
+attach dwctwo at obio with rkdwctwo
+file arch/arm/rockchip/rockchip_dwctwo.c rkdwctwo needs-flag
+
+# Console parameters
+defparam opt_rockchip.h CONADDR
+defparam opt_rockchip.h CONSPEED
+defparam opt_rockchip.h CONMODE
+
+# Memory parameters
+defparam opt_rockchip.h MEMSIZE
Index: src/sys/arch/arm/rockchip/obio.c
diff -u /dev/null src/sys/arch/arm/rockchip/obio.c:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/obio.c Fri Dec 26 16:53:33 2014
@@ -0,0 +1,201 @@
+/* $NetBSD: obio.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+
+/*
+ * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: obio.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+
+#include <machine/cpu.h>
+#include <sys/bus.h>
+
+#include <arm/mainbus/mainbus.h>
+#include <arm/rockchip/rockchip_reg.h>
+#include <arm/rockchip/rockchip_var.h>
+
+
+#include "locators.h"
+
+int obio_match(device_t, cfdata_t, void *);
+void obio_attach(device_t, device_t, void *);
+
+CFATTACH_DECL_NEW(obio, 0,
+ obio_match, obio_attach, NULL, NULL);
+
+int obio_print(void *, const char *);
+int obio_search(device_t, cfdata_t, const int *, void *);
+
+void obio_init_grf(void);
+void obio_iomux(int, int);
+void obio_init_gpio(void);
+void obio_swporta(int, int, int);
+
+/* there can be only one */
+bool obio_found;
+
+int
+obio_match(device_t parent, cfdata_t cf, void *aux)
+{
+
+ if (obio_found)
+ return 0;
+ return 1;
+}
+
+void
+obio_attach(device_t parent, device_t self, void *aux)
+{
+ obio_found = true;
+
+ aprint_naive("\n");
+ aprint_normal(": On-board I/O\n");
+
+ obio_init_grf();
+ obio_init_gpio();
+
+ /*
+ * Attach all on-board devices as described in the kernel
+ * configuration file.
+ */
+ config_search_ia(obio_search, self, "obio", NULL);
+}
+
+int
+obio_print(void *aux, const char *pnp)
+{
+ struct obio_attach_args *obio = aux;
+
+ aprint_normal(": addr 0x%08lx", obio->obio_addr);
+ aprint_normal("-0x%08lx", obio->obio_addr + (obio->obio_size - 1));
+ if (obio->obio_width != OBIOCF_WIDTH_DEFAULT)
+ aprint_normal(" width %d", obio->obio_width);
+ if (obio->obio_intr != OBIOCF_INTR_DEFAULT)
+ aprint_normal(" intr %d", obio->obio_intr);
+ aprint_normal(" mult %d", obio->obio_mult);
+
+ return UNCONF;
+}
+
+int
+obio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
+{
+ struct obio_attach_args obio;
+
+ obio.obio_addr = cf->cf_loc[OBIOCF_ADDR];
+ obio.obio_size = cf->cf_loc[OBIOCF_SIZE];
+ obio.obio_width = cf->cf_loc[OBIOCF_WIDTH];
+ obio.obio_intr = cf->cf_loc[OBIOCF_INTR];
+ obio.obio_mult = cf->cf_loc[OBIOCF_MULT];
+ obio.obio_dmat = &rockchip_bus_dma_tag;
+
+
+ switch (cf->cf_loc[OBIOCF_MULT]) {
+ case 1:
+ obio.obio_iot = &rockchip_bs_tag;
+ break;
+ case 4:
+ obio.obio_iot = &rockchip_a4x_bs_tag;
+ break;
+ default:
+ panic("Unsupported EMIFS multiplier.");
+ break;
+ }
+ if (config_match(parent, cf, &obio) > 0) {
+ config_attach(parent, cf, &obio, obio_print);
+ }
+ return 0;
+}
+
+#define GRF_GPIO3A_IOMUX_OFFSET 0x0090
+#define GRF_GPIO3B_IOMUX_OFFSET 0x0094
+#define GRF_GPIO3C_IOMUX_OFFSET 0x0098
+#define GRF_GPIO3D_IOMUX_OFFSET 0x009C
+
+void obio_init_grf(void)
+{
+ obio_iomux(GRF_GPIO3A_IOMUX_OFFSET, 0xffff5555);
+ obio_iomux(GRF_GPIO3B_IOMUX_OFFSET, 0xffff0004);
+ obio_iomux(GRF_GPIO3D_IOMUX_OFFSET, 0xffff1400);
+}
+
+void obio_iomux(int offset, int new)
+{
+ bus_space_handle_t bh;
+ bus_space_tag_t bt = &rockchip_bs_tag;
+ int old, renew;
+
+ if (bus_space_map(bt, ROCKCHIP_GRF_BASE, ROCKCHIP_GRF_SIZE, 0, &bh))
+ panic("GRF can not be mapped.");
+
+ old = bus_space_read_4(bt, bh, offset);
+ bus_space_write_4(bt, bh, offset, (old | new | 0xffff0000));
+ renew = bus_space_read_4(bt, bh, offset);
+
+ printf("grf iomux: old %08x, new %08x, renew %08x\n", old, new, renew);
+
+ bus_space_unmap(bt, bh, ROCKCHIP_GRF_SIZE);
+}
+
+#define GPIO_SWPORTA_DR_OFFSET 0x00
+#define GPIO_SWPORTA_DD_OFFSET 0x04
+
+void obio_init_gpio(void)
+{
+ obio_swporta(ROCKCHIP_GPIO0_BASE, GPIO_SWPORTA_DR_OFFSET, __BIT(3));
+ obio_swporta(ROCKCHIP_GPIO0_BASE, GPIO_SWPORTA_DD_OFFSET, __BIT(3));
+}
+
+void obio_swporta(int gpio_base, int offset, int new)
+{
+ bus_space_handle_t bh;
+ bus_space_tag_t bt = &rockchip_bs_tag;
+ int old, renew;
+ int gpio_size = 0x100; /* XXX */
+
+ if (bus_space_map(bt, gpio_base, gpio_size, 0, &bh))
+ panic("gpio can not be mapped.");
+
+ old = bus_space_read_4(bt, bh, offset);
+ bus_space_write_4(bt, bh, offset, old | new);
+ renew = bus_space_read_4(bt, bh, offset);
+
+ printf("gpio: 0x%08x 0x%08x -> 0x%08x\n", gpio_base + offset, old, renew);
+
+ bus_space_unmap(bt, bh, gpio_size);
+}
Index: src/sys/arch/arm/rockchip/obio_com.c
diff -u /dev/null src/sys/arch/arm/rockchip/obio_com.c:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/obio_com.c Fri Dec 26 16:53:33 2014
@@ -0,0 +1,146 @@
+/* $NetBSD: obio_com.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+
+/* based on omap/obio_com.c */
+
+/*
+ * Based on arch/arm/omap/omap_com.c
+ *
+ * Copyright 2003 Wasabi Systems, Inc.
+ * OMAP support Copyright (c) 2007 Microsoft
+ * All rights reserved.
+ *
+ * Written by Steve C. Woodford for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: obio_com.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
+
+#include "opt_rockchip.h"
+/*#include "opt_com.h"*/
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/termios.h>
+
+#include <machine/intr.h>
+#include <sys/bus.h>
+
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+
+#include <arm/rockchip/rockchip_var.h>
+#include <arm/rockchip/rockchip_reg.h>
+
+#include "locators.h"
+
+static int obiouart_match(device_t, cfdata_t, void *);
+static void obiouart_attach(device_t, device_t, void *);
+
+struct com_obio_softc {
+ struct com_softc sc_sc;
+ void *sc_ih;
+};
+
+CFATTACH_DECL_NEW(obiouart, sizeof(struct com_obio_softc),
+ obiouart_match, obiouart_attach, NULL, NULL);
+
+static int
+obiouart_match(device_t parent, cfdata_t cf, void *aux)
+{
+ struct obio_attach_args *obio = aux;
+ bus_space_handle_t bh;
+ int rv;
+ if (obio->obio_addr == OBIOCF_ADDR_DEFAULT)
+ panic("obiouart must have addr specified in config.");
+#if 0
+ /*
+ * XXX this should be ifdefed on a board-dependent switch
+ * We don't know what is the irq for com0 on the sdp2430
+ */
+ if (obio->obio_intr == OBIOCF_INTR_DEFAULT)
+ panic("obiouart must have intr specified in config.");
+#endif
+
+ if (obio->obio_size == OBIOCF_SIZE_DEFAULT)
+ obio->obio_size = ROCKCHIP_UART_SIZE;
+
+ if (com_is_console(obio->obio_iot, obio->obio_addr, NULL))
+ return 1;
+
+ if (bus_space_map(obio->obio_iot, obio->obio_addr, obio->obio_size,
+ 0, &bh))
+ return 1;
+
+ rv = comprobe1(obio->obio_iot, bh);
+
+ bus_space_unmap(obio->obio_iot, bh, obio->obio_size);
+
+ return rv;
+}
+
+static void
+obiouart_attach(device_t parent, device_t self, void *aux)
+{
+ struct com_obio_softc *osc = device_private(self);
+ struct com_softc *sc = &osc->sc_sc;
+ struct obio_attach_args *obio = aux;
+ bus_space_tag_t iot;
+ bus_space_handle_t ioh = 0;
+ bus_addr_t iobase;
+
+
+ sc->sc_dev = self;
+
+ iot = obio->obio_iot;
+ iobase = obio->obio_addr;
+ sc->sc_frequency = ROCKCHIP_UART_FREQ;
+ sc->sc_type = COM_TYPE_NORMAL;
+
+ if (com_is_console(iot, iobase, &ioh) == 0 &&
+ bus_space_map(iot, iobase, obio->obio_size, 0, &ioh)) {
+ panic(": can't map registers\n");
+ return;
+ }
+ COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
+
+ com_attach_subr(sc);
+ aprint_naive("\n");
+
+#if 1
+ KASSERT(obio->obio_intr != OBIOCF_INTR_DEFAULT);
+ osc->sc_ih = intr_establish(obio->obio_intr, IPL_SERIAL, IST_EDGE,
+ comintr, sc);
+ if (osc->sc_ih == NULL)
+ panic("%s: failed to establish interrup %d",
+ device_xname(self), obio->obio_intr);
+#endif
+}
Index: src/sys/arch/arm/rockchip/rockchip_dma.c
diff -u /dev/null src/sys/arch/arm/rockchip/rockchip_dma.c:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/rockchip_dma.c Fri Dec 26 16:53:33 2014
@@ -0,0 +1,63 @@
+/* $NetBSD: rockchip_dma.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+
+/* adapted from:
+ * NetBSD: pxa2x0_dma.c,v 1.4 2005/12/11 12:16:51 christos Exp
+ */
+
+/*
+ * Copyright (c) 2002 Genetec Corporation. All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Genetec Corporation.
+ * 4. The name of Genetec Corporation may not be used to endorse or
+ * promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * bus dma tag for PXA2[15]0 processor.
+ * (Currently used only for LCD frame buffer)
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rockchip_dma.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/mbuf.h>
+
+#include <uvm/uvm_extern.h>
+
+#define _ARM32_BUS_DMA_PRIVATE
+#include <sys/bus.h>
+
+struct arm32_bus_dma_tag rockchip_bus_dma_tag = {
+ _BUS_DMAMAP_FUNCS,
+ _BUS_DMAMEM_FUNCS,
+ _BUS_DMATAG_FUNCS,
+};
Index: src/sys/arch/arm/rockchip/rockchip_dwctwo.c
diff -u /dev/null src/sys/arch/arm/rockchip/rockchip_dwctwo.c:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/rockchip_dwctwo.c Fri Dec 26 16:53:33 2014
@@ -0,0 +1,171 @@
+/* $NetBSD: rockchip_dwctwo.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2013 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rockchip_dwctwo.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/mutex.h>
+#include <sys/bus.h>
+#include <sys/workqueue.h>
+
+#include <arm/rockchip/rockchip_reg.h>
+#include <arm/rockchip/rockchip_var.h>
+
+#include <dev/usb/usb.h>
+#include <dev/usb/usbdi.h>
+#include <dev/usb/usbdivar.h>
+#include <dev/usb/usb_mem.h>
+
+#include <dwc2/dwc2var.h>
+
+#include <dwc2/dwc2.h>
+#include "dwc2_core.h"
+
+struct rkdwc2_softc {
+ struct dwc2_softc sc_dwc2;
+
+ void *sc_ih;
+};
+
+static struct dwc2_core_params rkdwc2_params = {
+ .otg_cap = 2, /* 0 - HNP/SRP capable */
+ .otg_ver = 0, /* 0 - 1.3 */
+ .dma_enable = 1, /* 1 - DMA (default, if available) */
+ .dma_desc_enable = 1, /* 1 - Descriptor DMA (default, if available) */
+ .speed = 0, /* 0 - High Speed */
+ .enable_dynamic_fifo = 1, /* 1 - Allow dynamic FIFO sizing (default, if available) */
+ .en_multiple_tx_fifo = 1, /* Specifies whether dedicated per-endpoint transmit FIFOs are enabled */
+ .host_rx_fifo_size = 520, /* 520 DWORDs */
+ .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
+ .host_perio_tx_fifo_size = 256, /* 256 DWORDs */
+ .max_transfer_size = 65535,/* 2047 to 65,535 */
+ .max_packet_count = 511, /* 15 to 511 */
+ .host_channels = 8, /* 1 to 16 */
+ .phy_type = 1, /* 1- UTMI+ Phy */
+ .phy_utmi_width = 8, /* 8 bits */
+ .phy_ulpi_ddr = 0, /* Single */
+ .phy_ulpi_ext_vbus = 0,
+ .i2c_enable = 0,
+ .ulpi_fs_ls = 0, /* 0 - No (default) */
+ .host_support_fs_ls_low_power = 0, /* 0 - Don't support low power mode (default) */
+ .host_ls_low_power_phy_clk = 0, /* 1 - 48 MHz default when phy_type is UTMI+ or ULPI*/
+ .ts_dline = 0, /* 0 - No (default) */
+ .reload_ctl = 0, /* 0 - No (default for core < 2.92a) */
+ .ahbcfg = 0x7, /* INCR16 */
+ .uframe_sched = 1, /* True to enable microframe scheduler */
+};
+
+static int rkdwc2_match(device_t, struct cfdata *, void *);
+static void rkdwc2_attach(device_t, device_t, void *);
+static void rkdwc2_deferred(device_t);
+
+CFATTACH_DECL_NEW(rkdwctwo, sizeof(struct rkdwc2_softc),
+ rkdwc2_match, rkdwc2_attach, NULL, NULL);
+
+/* ARGSUSED */
+static int
+rkdwc2_match(device_t parent, struct cfdata *match, void *aux)
+{
+#if 0
+ struct obio_attach_args *obio = aux;
+
+ if (strcmp(obio->obio_name, "dwctwo") != 0)
+ return 0;
+#endif
+ return 1;
+}
+
+/* ARGSUSED */
+static void
+rkdwc2_attach(device_t parent, device_t self, void *aux)
+{
+ struct rkdwc2_softc *sc = device_private(self);
+ struct obio_attach_args *obio = aux;
+ int error;
+
+ sc->sc_dwc2.sc_dev = self;
+
+ sc->sc_dwc2.sc_iot = obio->obio_iot;
+ sc->sc_dwc2.sc_bus.dmatag = obio->obio_dmat;
+ sc->sc_dwc2.sc_params = &rkdwc2_params;
+
+ error = bus_space_map(obio->obio_iot, obio->obio_addr, obio->obio_size, 0,
+ &sc->sc_dwc2.sc_ioh);
+ if (error) {
+ aprint_error_dev(self,
+ "can't map registers for %s: %d\n", obio->obio_name, error);
+ return;
+ }
+
+ aprint_naive(": USB controller\n");
+ aprint_normal(": USB controller\n");
+
+ sc->sc_ih = intr_establish(obio->obio_intr, IPL_SCHED,
+ IST_LEVEL, dwc2_intr, &sc->sc_dwc2);
+#if 0
+ IST_EDGE, dwc2_intr, &sc->sc_dwc2);
+#endif
+
+ if (sc->sc_ih == NULL) {
+ aprint_error_dev(self, "failed to establish interrupt %d\n",
+ obio->obio_intr);
+ goto fail;
+ }
+ config_defer(self, rkdwc2_deferred);
+
+ return;
+
+fail:
+ if (sc->sc_ih) {
+ intr_disestablish(sc->sc_ih);
+ sc->sc_ih = NULL;
+ }
+ bus_space_unmap(sc->sc_dwc2.sc_iot, sc->sc_dwc2.sc_ioh, obio->obio_size);
+}
+
+static void
+rkdwc2_deferred(device_t self)
+{
+ struct rkdwc2_softc *sc = device_private(self);
+ int error;
+
+ error = dwc2_init(&sc->sc_dwc2);
+ if (error != 0) {
+ aprint_error_dev(self, "couldn't initialize host, error=%d\n",
+ error);
+ return;
+ }
+ sc->sc_dwc2.sc_child = config_found(sc->sc_dwc2.sc_dev,
+ &sc->sc_dwc2.sc_bus, usbctlprint);
+}
Index: src/sys/arch/arm/rockchip/rockchip_intr.h
diff -u /dev/null src/sys/arch/arm/rockchip/rockchip_intr.h:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/rockchip_intr.h Fri Dec 26 16:53:33 2014
@@ -0,0 +1,41 @@
+/* $NetBSD: rockchip_intr.h,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Hiroshi Tokuda
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ROCKCHIP_ROCKCHIP_INTR_H_
+#define _ARM_ROCKCHIP_ROCKCHIP_INTR_H_
+
+#define PIC_MAXSOURCES (32+128)
+#define PIC_MAXMAXSOURCES (PIC_MAXSOURCES+6*32)
+
+#include <arm/cortex/gic_intr.h>
+#include <arm/cortex/a9tmr_intr.h> /* A9 Timer PPIs */
+
+#endif /* _ARM_ROCKCHIP_ROCKCHIP_INTR_H_ */
Index: src/sys/arch/arm/rockchip/rockchip_reg.h
diff -u /dev/null src/sys/arch/arm/rockchip/rockchip_reg.h:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/rockchip_reg.h Fri Dec 26 16:53:33 2014
@@ -0,0 +1,84 @@
+/* $NetBSD: rockchip_reg.h,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Hiroshi Tokuda
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ROCKCHIP_ROCKCHIP_REG_H_
+#define _ARM_ROCKCHIP_ROCKCHIP_REG_H_
+
+#define CONSADDR_VA ((CONSADDR - ROCKCHIP_CORE1_BASE) + ROCKCHIP_CORE1_VBASE)
+
+#define ROCKCHIP_REF_FREQ 24000000L /* 24MHz */
+#define ROCKCHIP_UART_FREQ ROCKCHIP_REF_FREQ
+#define ROCKCHIP_UART_SIZE 0x400
+
+#define ROCKCHIP_CORE0_BASE 0x10000000
+#define ROCKCHIP_CORE0_VBASE 0xFEA00000
+#define ROCKCHIP_CORE0_SIZE 0x00300000
+
+#define ROCKCHIP_OTG_BASE 0x10180000
+#define ROCKCHIP_OTG_SIZE 0x40000
+#define ROCKCHIP_USB_BASE 0x101C0000
+#define ROCKCHIP_USB_SIZE 0x40000
+#define ROCKCHIP_UART0_BASE 0x10124000
+#define ROCKCHIP_UART0_SIZE 0x400
+#define ROCKCHIP_UART1_BASE 0x10126000
+#define ROCKCHIP_UART1_SIZE 0x400
+#define ROCKCHIP_PL310_BASE 0x10138000
+#define ROCKCHIP_PL310_SIZE 0x1000
+#define ROCKCHIP_GICC_BASE 0x1013C100
+#define ROCKCHIP_GICC_SIZE 0x100
+#define ROCKCHIP_A9TMR_BASE 0x1013C200
+#define ROCKCHIP_A9TMR_SIZE 0x100
+#define ROCKCHIP_A9WDT_BASE 0x1013C600
+#define ROCKCHIP_A9WDT_SIZE 0x20
+#define ROCKCHIP_GICD_BASE 0x1013D000
+#define ROCKCHIP_GICD_SIZE 0x1000
+
+#define ROCKCHIP_CORE1_BASE 0x20000000
+#define ROCKCHIP_CORE1_VBASE 0xFED00000
+#define ROCKCHIP_CORE1_SIZE 0x00100000
+
+#define ROCKCHIP_GRF_BASE 0x20008000
+#define ROCKCHIP_GRF_SIZE 0x2000
+
+#define ROCKCHIP_UART2_BASE 0x20064000
+#define ROCKCHIP_UART2_SIZE 0x400
+#define ROCKCHIP_UART3_BASE 0x20068000
+#define ROCKCHIP_UART3_SIZE 0x400
+#define ROCKCHIP_GPIO0_BASE 0x2000A000
+#define ROCKCHIP_GPIO0_SIZE 0x100
+#define ROCKCHIP_GPIO1_BASE 0x2003C000
+#define ROCKCHIP_GPIO1_SIZE 0x100
+#define ROCKCHIP_GPIO2_BASE 0x2003E000
+#define ROCKCHIP_GPIO2_SIZE 0x100
+#define ROCKCHIP_GPIO3_BASE 0x20080000
+#define ROCKCHIP_GPIO3_SIZE 0x100
+
+#endif /* _ARM_ROCKCHIP_ROCKCHIP_REG_H_ */
Index: src/sys/arch/arm/rockchip/rockchip_space.c
diff -u /dev/null src/sys/arch/arm/rockchip/rockchip_space.c:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/rockchip_space.c Fri Dec 26 16:53:33 2014
@@ -0,0 +1,425 @@
+/* $NetBSD: rockchip_space.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2012 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Nick Hudson
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rockchip_space.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <sys/bus.h>
+
+/* Prototypes for all the bus_space structure functions */
+bs_protos(rockchip);
+bs_protos(rockchip_a4x);
+bs_protos(a4x);
+bs_protos(bs_notimpl);
+bs_protos(generic);
+bs_protos(generic_armv4);
+
+#if __ARMEB__
+#define NSWAP(n) n ## _swap
+#else
+#define NSWAP(n) n
+#endif
+
+struct bus_space rockchip_bs_tag = {
+ /* cookie */
+ (void *) 0,
+
+ /* mapping/unmapping */
+ rockchip_bs_map,
+ rockchip_bs_unmap,
+ rockchip_bs_subregion,
+
+ /* allocation/deallocation */
+ rockchip_bs_alloc, /* not implemented */
+ rockchip_bs_free, /* not implemented */
+
+ /* get kernel virtual address */
+ rockchip_bs_vaddr,
+
+ /* mmap */
+ rockchip_bs_mmap,
+
+ /* barrier */
+ rockchip_bs_barrier,
+
+ /* read (single) */
+ generic_bs_r_1,
+ NSWAP(generic_armv4_bs_r_2),
+ NSWAP(generic_bs_r_4),
+ bs_notimpl_bs_r_8,
+
+ /* read multiple */
+ generic_bs_rm_1,
+ NSWAP(generic_armv4_bs_rm_2),
+ NSWAP(generic_bs_rm_4),
+ bs_notimpl_bs_rm_8,
+
+ /* read region */
+ generic_bs_rr_1,
+ NSWAP(generic_armv4_bs_rr_2),
+ NSWAP(generic_bs_rr_4),
+ bs_notimpl_bs_rr_8,
+
+ /* write (single) */
+ generic_bs_w_1,
+ NSWAP(generic_armv4_bs_w_2),
+ NSWAP(generic_bs_w_4),
+ bs_notimpl_bs_w_8,
+
+ /* write multiple */
+ generic_bs_wm_1,
+ NSWAP(generic_armv4_bs_wm_2),
+ NSWAP(generic_bs_wm_4),
+ bs_notimpl_bs_wm_8,
+
+ /* write region */
+ generic_bs_wr_1,
+ NSWAP(generic_armv4_bs_wr_2),
+ NSWAP(generic_bs_wr_4),
+ bs_notimpl_bs_wr_8,
+
+ /* set multiple */
+ bs_notimpl_bs_sm_1,
+ bs_notimpl_bs_sm_2,
+ bs_notimpl_bs_sm_4,
+ bs_notimpl_bs_sm_8,
+
+ /* set region */
+ generic_bs_sr_1,
+ NSWAP(generic_armv4_bs_sr_2),
+ bs_notimpl_bs_sr_4,
+ bs_notimpl_bs_sr_8,
+
+ /* copy */
+ bs_notimpl_bs_c_1,
+ generic_armv4_bs_c_2,
+ bs_notimpl_bs_c_4,
+ bs_notimpl_bs_c_8,
+
+#ifdef __BUS_SPACE_HAS_STREAM_METHODS
+ /* read (single) */
+ generic_bs_r_1,
+ NSWAP(generic_armv4_bs_r_2),
+ NSWAP(generic_bs_r_4),
+ bs_notimpl_bs_r_8,
+
+ /* read multiple */
+ generic_bs_rm_1,
+ NSWAP(generic_armv4_bs_rm_2),
+ NSWAP(generic_bs_rm_4),
+ bs_notimpl_bs_rm_8,
+
+ /* read region */
+ generic_bs_rr_1,
+ NSWAP(generic_armv4_bs_rr_2),
+ NSWAP(generic_bs_rr_4),
+ bs_notimpl_bs_rr_8,
+
+ /* write (single) */
+ generic_bs_w_1,
+ NSWAP(generic_armv4_bs_w_2),
+ NSWAP(generic_bs_w_4),
+ bs_notimpl_bs_w_8,
+
+ /* write multiple */
+ generic_bs_wm_1,
+ NSWAP(generic_armv4_bs_wm_2),
+ NSWAP(generic_bs_wm_4),
+ bs_notimpl_bs_wm_8,
+
+ /* write region */
+ generic_bs_wr_1,
+ NSWAP(generic_armv4_bs_wr_2),
+ NSWAP(generic_bs_wr_4),
+ bs_notimpl_bs_wr_8,
+#endif
+};
+
+struct bus_space rockchip_a4x_bs_tag = {
+ /* cookie */
+ (void *) 0,
+
+ /* mapping/unmapping */
+ rockchip_bs_map,
+ rockchip_bs_unmap,
+ rockchip_a4x_bs_subregion,
+
+ /* allocation/deallocation */
+ rockchip_bs_alloc, /* not implemented */
+ rockchip_bs_free, /* not implemented */
+
+ /* get kernel virtual address */
+ rockchip_bs_vaddr,
+
+ /* mmap */
+ rockchip_a4x_bs_mmap,
+
+ /* barrier */
+ rockchip_bs_barrier,
+
+ /* read (single) */
+ a4x_bs_r_1,
+ NSWAP(a4x_bs_r_2),
+ NSWAP(a4x_bs_r_4),
+ bs_notimpl_bs_r_8,
+
+ /* read multiple */
+ a4x_bs_rm_1,
+ NSWAP(a4x_bs_rm_2),
+ NSWAP(a4x_bs_rm_4),
+ bs_notimpl_bs_rm_8,
+
+ /* read region */
+ bs_notimpl_bs_rr_1,
+ bs_notimpl_bs_rr_2,
+ bs_notimpl_bs_rr_4,
+ bs_notimpl_bs_rr_8,
+
+ /* write (single) */
+ a4x_bs_w_1,
+ NSWAP(a4x_bs_w_2),
+ NSWAP(a4x_bs_w_4),
+ bs_notimpl_bs_w_8,
+
+ /* write multiple */
+ a4x_bs_wm_1,
+ NSWAP(a4x_bs_wm_2),
+ NSWAP(a4x_bs_wm_4),
+ bs_notimpl_bs_wm_8,
+
+ /* write region */
+ bs_notimpl_bs_wr_1,
+ bs_notimpl_bs_wr_2,
+ bs_notimpl_bs_wr_4,
+ bs_notimpl_bs_wr_8,
+
+ /* set multiple */
+ bs_notimpl_bs_sm_1,
+ bs_notimpl_bs_sm_2,
+ bs_notimpl_bs_sm_4,
+ bs_notimpl_bs_sm_8,
+
+ /* set region */
+ bs_notimpl_bs_sr_1,
+ bs_notimpl_bs_sr_2,
+ bs_notimpl_bs_sr_4,
+ bs_notimpl_bs_sr_8,
+
+ /* copy */
+ bs_notimpl_bs_c_1,
+ bs_notimpl_bs_c_2,
+ bs_notimpl_bs_c_4,
+ bs_notimpl_bs_c_8,
+
+#ifdef __BUS_SPACE_HAS_STREAM_METHODS
+ /* read (single) */
+ a4x_bs_r_1,
+ NSWAP(a4x_bs_r_2),
+ NSWAP(a4x_bs_r_4),
+ bs_notimpl_bs_r_8,
+
+ /* read multiple */
+ a4x_bs_rm_1,
+ NSWAP(a4x_bs_rm_2),
+ NSWAP(a4x_bs_rm_4),
+ bs_notimpl_bs_rm_8,
+
+ /* read region */
+ a4x_bs_rr_1,
+ NSWAP(a4x_bs_rr_2),
+ NSWAP(a4x_bs_rr_4),
+ bs_notimpl_bs_rr_8,
+
+ /* write (single) */
+ a4x_bs_w_1,
+ NSWAP(a4x_bs_w_2),
+ NSWAP(a4x_bs_w_4),
+ bs_notimpl_bs_w_8,
+
+ /* write multiple */
+ a4x_bs_wm_1,
+ NSWAP(a4x_bs_wm_2),
+ NSWAP(a4x_bs_wm_4),
+ bs_notimpl_bs_wm_8,
+
+ /* write region */
+ a4x_bs_wr_1,
+ NSWAP(a4x_bs_wr_2),
+ NSWAP(a4x_bs_wr_4),
+ bs_notimpl_bs_wr_8,
+#endif
+};
+
+int
+rockchip_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flag,
+ bus_space_handle_t *bshp)
+{
+ u_long startpa, endpa, pa;
+ const struct pmap_devmap *pd;
+ vaddr_t va;
+
+ if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) {
+ /* Device was statically mapped. */
+ *bshp = pd->pd_va + (bpa - pd->pd_pa);
+ return 0;
+ }
+
+ startpa = trunc_page(bpa);
+ endpa = round_page(bpa + size);
+
+ /* XXX use extent manager to check duplicate mapping */
+
+ va = uvm_km_alloc(kernel_map, endpa - startpa, 0,
+ UVM_KMF_VAONLY | UVM_KMF_NOWAIT | UVM_KMF_COLORMATCH);
+ if (!va)
+ return ENOMEM;
+
+ *bshp = (bus_space_handle_t)(va + (bpa - startpa));
+
+ const int pmapflags =
+ (flag & (BUS_SPACE_MAP_CACHEABLE|BUS_SPACE_MAP_PREFETCHABLE))
+ ? 0
+ : PMAP_NOCACHE;
+ for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
+ pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, pmapflags);
+ }
+ pmap_update(pmap_kernel());
+
+ return 0;
+}
+
+void
+rockchip_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+ vaddr_t va;
+ vsize_t sz;
+
+ if (pmap_devmap_find_va(bsh, size) != NULL) {
+ /* Device was statically mapped; nothing to do. */
+ return;
+ }
+
+ va = trunc_page(bsh);
+ sz = round_page(bsh + size) - va;
+
+ pmap_kremove(va, sz);
+ pmap_update(pmap_kernel());
+ uvm_km_free(kernel_map, va, sz, UVM_KMF_VAONLY);
+}
+
+
+int
+rockchip_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ bus_size_t size, bus_space_handle_t *nbshp)
+{
+
+ *nbshp = bsh + offset;
+ return (0);
+}
+
+int
+rockchip_a4x_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ bus_size_t size, bus_space_handle_t *nbshp)
+{
+
+ *nbshp = bsh + 4 * offset;
+ return (0);
+}
+
+void
+rockchip_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
+ bus_size_t len, int flags)
+{
+ flags &= BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE;
+
+ if (flags) {
+ /* Issue an ARM11 Data Syncronisation Barrier (DSB) */
+#ifdef _ARM_ARCH_7
+ __asm __volatile("dsb");
+#else
+ __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)
+ : "memory");
+#endif
+ return;
+ }
+
+}
+
+void *
+rockchip_bs_vaddr(void *t, bus_space_handle_t bsh)
+{
+
+ return (void *)bsh;
+}
+
+paddr_t
+rockchip_bs_mmap(void *t, bus_addr_t bpa, off_t offset, int prot, int flags)
+{
+ paddr_t bus_flags = 0;
+
+ if (flags & BUS_SPACE_MAP_PREFETCHABLE)
+ bus_flags |= ARM32_MMAP_WRITECOMBINE;
+
+ return (arm_btop(bpa + offset) | bus_flags);
+}
+
+paddr_t
+rockchip_a4x_bs_mmap(void *t, bus_addr_t bpa, off_t offset, int prot, int flags)
+{
+ paddr_t bus_flags = 0;
+
+ if (flags & BUS_SPACE_MAP_PREFETCHABLE)
+ bus_flags |= ARM32_MMAP_WRITECOMBINE;
+
+ return (arm_btop(bpa + 4 * offset) | bus_flags);
+}
+
+int
+rockchip_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
+ bus_size_t size, bus_size_t alignment, bus_size_t boundary, int flags,
+ bus_addr_t *bpap, bus_space_handle_t *bshp)
+{
+
+ panic("%s(): not implemented\n", __func__);
+}
+
+void
+rockchip_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
+{
+
+ panic("%s(): not implemented\n", __func__);
+}
Index: src/sys/arch/arm/rockchip/rockchip_var.h
diff -u /dev/null src/sys/arch/arm/rockchip/rockchip_var.h:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/rockchip_var.h Fri Dec 26 16:53:33 2014
@@ -0,0 +1,53 @@
+/* $NetBSD: rockchip_var.h,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Hiroshi Tokuda
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_ROCKCHIP_ROCKCHIP_VAR_H_
+#define _ARM_ROCKCHIP_ROCKCHIP_VAR_H_
+
+#include <sys/types.h>
+#include <sys/bus.h>
+
+struct obio_attach_args {
+ bus_space_tag_t obio_iot; /* bus space tag */
+ bus_addr_t obio_addr; /* address of device */
+ bus_size_t obio_size; /* size of device */
+ int obio_intr; /* irq */
+ int obio_width; /* bus width */
+ unsigned int obio_mult; /* multiplier */
+ bus_dma_tag_t obio_dmat;
+ const char *obio_name;
+};
+
+extern struct bus_space rockchip_bs_tag;
+extern struct bus_space rockchip_a4x_bs_tag;
+extern struct arm32_bus_dma_tag rockchip_bus_dma_tag;
+
+#endif /* _ARM_ROCKCHIP_ROCKCHIP_VAR_H_ */
Index: src/sys/arch/evbarm/conf/ROCKCHIP
diff -u /dev/null src/sys/arch/evbarm/conf/ROCKCHIP:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/evbarm/conf/ROCKCHIP Fri Dec 26 16:53:33 2014
@@ -0,0 +1,221 @@
+#
+# $NetBSD: ROCKCHIP,v 1.1 2014/12/26 16:53:33 jmcneill Exp $
+#
+# Rockchip RK3066/RK3188 based SBC (Single Board Computer)
+#
+
+include "arch/evbarm/conf/std.rockchip"
+
+# estimated number of users
+
+maxusers 32
+
+# Standard system options
+
+options RTC_OFFSET=0 # hardware clock is this many mins. west of GMT
+#options NTP # NTP phase/frequency locked loop
+
+# CPU options
+
+options CPU_CORTEXA9
+options PMAPCOUNTERS
+
+# Architecture options
+
+# File systems
+
+file-system FFS # UFS
+#file-system LFS # log-structured file system
+file-system MFS # memory file system
+file-system NFS # Network file system
+#file-system ADOSFS # AmigaDOS-compatible file system
+#file-system EXT2FS # second extended file system (linux)
+#file-system CD9660 # ISO 9660 + Rock Ridge file system
+#file-system MSDOSFS # MS-DOS file system
+#file-system FDESC # /dev/fd
+#file-system KERNFS # /kern
+#file-system NULLFS # loopback file system
+#file-system PROCFS # /proc
+#file-system PUFFS # Userspace file systems (e.g. ntfs-3g & sshfs)
+#file-system UMAPFS # NULLFS + uid and gid remapping
+#file-system UNION # union file system
+file-system TMPFS # memory file system
+file-system PTYFS # /dev/pts/N support
+
+# File system options
+#options QUOTA # legacy UFS quotas
+#options QUOTA2 # new, in-filesystem UFS quotas
+#options FFS_EI # FFS Endian Independant support
+#options NFSSERVER
+#options WAPBL # File system journaling support - Experimental
+#options FFS_NO_SNAPSHOT # No FFS snapshot support
+
+# Networking options
+
+#options GATEWAY # packet forwarding
+options INET # IP + ICMP + TCP + UDP
+#options INET6 # IPV6
+#options IPSEC # IP security
+#options IPSEC_DEBUG # debug for IP security
+#options MROUTING # IP multicast routing
+#options PIM # Protocol Independent Multicast
+#options NETATALK # AppleTalk networking
+#options PPP_BSDCOMP # BSD-Compress compression support for PPP
+#options PPP_DEFLATE # Deflate compression support for PPP
+#options PPP_FILTER # Active filter support for PPP (requires bpf)
+#options TCP_DEBUG # Record last TCP_NDEBUG packets with SO_DEBUG
+
+options NFS_BOOT_BOOTP
+#options NFS_BOOT_DHCP
+#options NFS_BOOT_BOOTSTATIC
+#options NFS_BOOTSTATIC_MYIP="\"192.168.1.4\""
+#options NFS_BOOTSTATIC_GWIP="\"192.168.1.1\""
+#options NFS_BOOTSTATIC_MASK="\"255.255.255.0\""
+#options NFS_BOOTSTATIC_SERVADDR="\"192.168.1.1\""
+#options NFS_BOOTSTATIC_SERVER="\"192.168.1.1:/nfs/sdp2430\""
+
+options NFS_BOOT_RWSIZE=1024
+
+# Compatibility options
+
+#options COMPAT_NETBSD32 # allow running arm (e.g. non-earm) binaries
+#options COMPAT_43 # 4.3BSD compatibility.
+#options COMPAT_09 # NetBSD 0.9,
+#options COMPAT_10 # NetBSD 1.0,
+#options COMPAT_11 # NetBSD 1.1,
+#options COMPAT_12 # NetBSD 1.2,
+#options COMPAT_13 # NetBSD 1.3,
+#options COMPAT_14 # NetBSD 1.4,
+#options COMPAT_15 # NetBSD 1.5,
+#options COMPAT_16 # NetBSD 1.6,
+#options COMPAT_20 # NetBSD 2.0,
+#options COMPAT_30 # NetBSD 3.0,
+#options COMPAT_40 # NetBSD 4.0,
+#options COMPAT_50 # NetBSD 5.0,
+#options COMPAT_60 # NetBSD 6.0, and
+options COMPAT_70 # NetBSD 7.0 binary compatibility.
+#options TCP_COMPAT_42 # 4.2BSD TCP/IP bug compat. Not recommended.
+#options COMPAT_BSDPTY # /dev/[pt]ty?? ptys.
+
+# Shared memory options
+
+#options SYSVMSG # System V-like message queues
+#options SYSVSEM # System V-like semaphores
+#options SEMMNI=10 # number of semaphore identifiers
+#options SEMMNS=60 # number of semaphores in system
+#options SEMUME=10 # max number of undo entries per process
+#options SEMMNU=30 # number of undo structures in system
+#options SYSVSHM # System V-like memory sharing
+
+# Device options
+
+#options MEMORY_DISK_HOOKS # boottime setup of ramdisk
+#options MEMORY_DISK_ROOT_SIZE=8192 # Size in blocks
+#options MEMORY_DISK_DYNAMIC
+#options MINIROOTSIZE=1000 # Size in blocks
+#options MEMORY_DISK_IS_ROOT # use memory disk as root
+#options MEMORY_DISK_FBFLAGS=RB_SINGLE
+
+# Miscellaneous kernel options
+options KTRACE # system call tracing, a la ktrace(1)
+#options KMEMSTATS # kernel memory statistics
+#options SCSIVERBOSE # Verbose SCSI errors
+#options MIIVERBOSE # Verbose MII autoconfuration messages
+#options DDB_KEYCODE=0x40
+#options USERCONF # userconf(4) support
+#options PIPE_SOCKETPAIR # smaller, but slower pipe(2)
+
+# Development and Debugging options
+
+#options PERFCTRS # performance counters
+options DIAGNOSTIC # internal consistency checks
+options DEBUG
+options LOCKDEBUG
+#options PMAP_DEBUG # Enable pmap_debug_level code
+#options IPKDB # remote kernel debugging
+options VERBOSE_INIT_ARM # verbose bootstraping messages
+options DDB # in-kernel debugger
+options DDB_ONPANIC=2
+options DDB_HISTORY_SIZE=100 # Enable history editing in DDB
+options DDB_COMMANDONENTER="bt"
+#options KGDB
+makeoptions DEBUG="-g" # compile full symbol table
+makeoptions COPY_SYMTAB=1
+
+config netbsd root on ? type ?
+
+# The main bus device
+mainbus0 at root
+
+# The boot cpu
+cpu0 at mainbus?
+
+# A9 core devices
+armperiph0 at mainbus?
+arml2cc0 at armperiph? # L2 Cache Controller
+armgic0 at armperiph? # Interrupt Controller
+a9tmr0 at armperiph? # Global Timer
+a9wdt0 at armperiph? # Watchdog
+
+# Specify the memory size in megabytes.
+options MEMSIZE=1024
+
+# L3 Interconnect
+#L3i0 at mainbus?
+
+# OBIO
+obio0 at mainbus?
+
+# On-board 16550 UARTs
+com0 at obio0 addr 0x20064000 size 0x400 intr 68 mult 4 # UART2 (console)
+options CONSADDR=0x20064000, CONSPEED=115200
+
+# SDHC
+#sdhc0 at obio0 addr 0x10214000 size 0x4000 intr 55
+#sdmmc* at sdhc?
+#ld* at sdmmc?
+
+#options SDHC_DEBUG
+#options SDMMC_DEBUG
+#options SDMMCCISDEBUG
+
+# On-board USB
+dwctwo0 at obio0 addr 0x10180000 size 0x40000 intr 48
+dwctwo1 at obio0 addr 0x101C0000 size 0x40000 intr 49
+usb* at dwctwo?
+
+include "dev/usb/usbdevices.config"
+midi* at midibus?
+
+rlphy* at mii? phy ?
+rgephy* at mii? phy ?
+ukphy* at mii? phy ?
+
+## USB Debugging options
+options USBVERBOSE
+#options USB_DEBUG
+#options EHCI_DEBUG
+#options OHCI_DEBUG
+#options UHUB_DEBUG
+#options DWC2_DEBUG
+
+# Pseudo-Devices
+
+# disk/mass storage pseudo-devices
+pseudo-device md # memory disk device (ramdisk)
+pseudo-device vnd # disk-like interface to files
+#pseudo-device fss # file system snapshot device
+pseudo-device drvctl # driver control
+#pseudo-device putter # for puffs and pud
+
+# network pseudo-devices
+pseudo-device bpfilter # Berkeley packet filter
+pseudo-device loop # network loopback
+#pseudo-device kttcp # network loopback
+
+# miscellaneous pseudo-devices
+pseudo-device pty # pseudo-terminals
+#options RND_COM
+#pseudo-device clockctl # user control of clock subsystem
+pseudo-device ksyms # /dev/ksyms
+pseudo-device lockstat # lock profiling
Index: src/sys/arch/evbarm/conf/files.rockchip
diff -u /dev/null src/sys/arch/evbarm/conf/files.rockchip:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/evbarm/conf/files.rockchip Fri Dec 26 16:53:33 2014
@@ -0,0 +1,10 @@
+# $NetBSD: files.rockchip,v 1.1 2014/12/26 16:53:33 jmcneill Exp $
+#
+# Rockchip configuration info
+#
+
+file arch/evbarm/rockchip/rockchip_machdep.c
+
+defparam opt_machdep.h BOOT_ARGS
+
+include "arch/arm/rockchip/files.rockchip"
Index: src/sys/arch/evbarm/conf/mk.rockchip
diff -u /dev/null src/sys/arch/evbarm/conf/mk.rockchip:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/evbarm/conf/mk.rockchip Fri Dec 26 16:53:33 2014
@@ -0,0 +1,33 @@
+# $NetBSD: mk.rockchip,v 1.1 2014/12/26 16:53:33 jmcneill Exp $
+CPPFLAGS+= -mcpu=cortex-a9
+
+SYSTEM_FIRST_OBJ= rockchip_start.o
+SYSTEM_FIRST_SFILE= ${THISARM}/rockchip/rockchip_start.S
+
+GENASSYM_EXTRAS+= ${THISARM}/rockchip/genassym.cf
+
+_OSRELEASE!= ${HOST_SH} $S/conf/osrelease.sh
+
+MKUBOOTIMAGEARGS= -A arm -T kernel
+MKUBOOTIMAGEARGS+= -a $(LOADADDRESS) -e $(LOADADDRESS)
+MKUBOOTIMAGEARGS+= -n "NetBSD/$(BOARDTYPE) ${_OSRELEASE}"
+MKUBOOTIMAGEARGS_NONE= ${MKUBOOTIMAGEARGS} -C none
+MKUBOOTIMAGEARGS_GZ= ${MKUBOOTIMAGEARGS} -C gz
+
+KERNEL_BASE_PHYS=0x60408000
+KERNEL_BASE_VIRT=0x80408000
+
+SYSTEM_LD_TAIL_EXTRA+=; \
+ echo ${OBJCOPY} -S -O binary $@ [email protected]; \
+ ${OBJCOPY} -S -O binary $@ [email protected]; \
+ echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} [email protected] [email protected]; \
+ ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_NONE} [email protected] [email protected]; \
+ echo ${TOOL_GZIP} -c [email protected] > [email protected]; \
+ ${TOOL_GZIP} -c [email protected] > [email protected]; \
+ echo ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} [email protected] [email protected]; \
+ ${TOOL_MKUBOOTIMAGE} ${MKUBOOTIMAGEARGS_GZ} [email protected] [email protected]
+
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.ub@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.bin.gz@}
+EXTRA_KERNELS+= ${KERNELS:@.KERNEL.@${.KERNEL.}.gz.ub@}
Index: src/sys/arch/evbarm/conf/std.rockchip
diff -u /dev/null src/sys/arch/evbarm/conf/std.rockchip:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/evbarm/conf/std.rockchip Fri Dec 26 16:53:33 2014
@@ -0,0 +1,27 @@
+# $NetBSD: std.rockchip,v 1.1 2014/12/26 16:53:33 jmcneill Exp $
+#
+
+machine evbarm arm
+include "arch/evbarm/conf/std.evbarm"
+
+include "arch/evbarm/conf/files.rockchip"
+
+options MODULAR
+options MODULAR_DEFAULT_AUTOLOAD
+options __HAVE_CPU_COUNTER
+options CORTEX_PMC
+options __HAVE_FAST_SOFTINTS # should be in types.h
+options ARM_HAS_VBAR
+options __HAVE_MM_MD_DIRECT_MAPPED_PHYS
+options TPIDRPRW_IS_CURCPU
+options KERNEL_BASE_EXT=0x80000000
+options FPU_VFP
+
+makeoptions LOADADDRESS="0x60408000"
+makeoptions BOARDTYPE="rockchip"
+makeoptions BOARDMKFRAG="${THISARM}/conf/mk.rockchip"
+
+options ARM_INTR_IMPL="<arch/arm/rockchip/rockchip_intr.h>"
+options ARM_GENERIC_TODR
+
+options COM_16750
Index: src/sys/arch/evbarm/rockchip/genassym.cf
diff -u /dev/null src/sys/arch/evbarm/rockchip/genassym.cf:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/evbarm/rockchip/genassym.cf Fri Dec 26 16:53:33 2014
@@ -0,0 +1,38 @@
+# $NetBSD: genassym.cf,v 1.1 2014/12/26 16:53:33 jmcneill Exp $
+
+#-
+# Copyright (c) 2013 The NetBSD Foundation, Inc.
+# All rights reserved.
+#
+# This code is derived from software contributed to The NetBSD Foundation
+# by Matt Thomas of 3am Software Foundry.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+# ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+# BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+include <dev/ic/ns16550reg.h>
+include <dev/ic/comreg.h>
+
+define LSR_TXRDY LSR_TXRDY
+define LSR_TSRE LSR_TSRE
+define COM_DATA com_data
+define COM_LSR com_lsr
Index: src/sys/arch/evbarm/rockchip/platform.h
diff -u /dev/null src/sys/arch/evbarm/rockchip/platform.h:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/evbarm/rockchip/platform.h Fri Dec 26 16:53:33 2014
@@ -0,0 +1,41 @@
+/* $NetBSD: platform.h,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+/*
+ * Copyright (c) 2007 Microsoft
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Microsoft
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _EVBARM_ROCKCHIP_PLATFORM_H
+#define _EVBARM_ROCKCHIP_PLATFORM_H
+
+#include <arm/rockchip/rockchip_reg.h>
+
+#define KERNEL_VM_BASE 0xc0000000
+#define KERNEL_VM_SIZE 0x20000000 /* 0x20000000 = 512MB */
+
+#define CONSADDR_VA ((CONSADDR - ROCKCHIP_CORE1_BASE) + ROCKCHIP_CORE1_VBASE)
+
+#endif /* _EVBARM_ROCKCHIP_PLATFORM_H */
Index: src/sys/arch/evbarm/rockchip/rockchip_machdep.c
diff -u /dev/null src/sys/arch/evbarm/rockchip/rockchip_machdep.c:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/evbarm/rockchip/rockchip_machdep.c Fri Dec 26 16:53:33 2014
@@ -0,0 +1,600 @@
+/* $NetBSD: rockchip_machdep.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+
+/*
+ * Machine dependent functions for kernel setup for TI OSK5912 board.
+ * Based on lubbock_machdep.c which in turn was based on iq80310_machhdep.c
+ *
+ * Copyright (c) 2002, 2003, 2005 Genetec Corporation. All rights reserved.
+ * Written by Hiroyuki Bessho for Genetec Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of Genetec Corporation may not be used to endorse or
+ * promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright (c) 2001 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Copyright (c) 1997,1998 Mark Brinicombe.
+ * Copyright (c) 1997,1998 Causality Limited.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Mark Brinicombe
+ * for the NetBSD Project.
+ * 4. The name of the company nor the name of the author may be used to
+ * endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * Copyright (c) 2007 Microsoft
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by Microsoft
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rockchip_machdep.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
+
+#include "opt_machdep.h"
+#include "opt_ddb.h"
+#include "opt_kgdb.h"
+#include "opt_ipkdb.h"
+#include "opt_md.h"
+#include "opt_com.h"
+#include "opt_rockchip.h"
+#include "opt_arm_debug.h"
+
+#include "com.h"
+#if 0
+#include "prcm.h"
+#include "sdhc.h"
+#include "ukbd.h"
+#endif
+#include "arml2cc.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+#include <sys/exec.h>
+#include <sys/kernel.h>
+#include <sys/ksyms.h>
+#include <sys/msgbuf.h>
+#include <sys/proc.h>
+#include <sys/reboot.h>
+#include <sys/termios.h>
+#include <sys/gpio.h>
+
+#include <uvm/uvm_extern.h>
+
+#include <sys/conf.h>
+#include <dev/cons.h>
+#include <dev/md.h>
+
+#include <machine/db_machdep.h>
+#include <ddb/db_sym.h>
+#include <ddb/db_extern.h>
+#ifdef KGDB
+#include <sys/kgdb.h>
+#endif
+
+#include <machine/bootconfig.h>
+#include <arm/armreg.h>
+#include <arm/undefined.h>
+
+#include <arm/arm32/machdep.h>
+#include <arm/mainbus/mainbus.h>
+
+#include <dev/ic/ns16550reg.h>
+#include <dev/ic/comreg.h>
+
+#include <arm/rockchip/rockchip_var.h>
+
+#ifdef CPU_CORTEXA9
+#include <arm/cortex/pl310_reg.h>
+#include <arm/cortex/scu_reg.h>
+
+#include <arm/cortex/a9tmr_var.h>
+#include <arm/cortex/pl310_var.h>
+#endif
+
+#if defined(CPU_CORTEXA7) || defined(CPU_CORTEXA15)
+#include <arm/cortex/gtmr_var.h>
+#endif
+
+#include <evbarm/include/autoconf.h>
+#include <evbarm/rockchip/platform.h>
+
+#include <dev/i2c/i2cvar.h>
+#include <dev/i2c/ddcreg.h>
+
+#include <dev/usb/ukbdvar.h>
+
+BootConfig bootconfig; /* Boot config storage */
+static char bootargs[MAX_BOOT_STRING];
+char *boot_args = NULL;
+char *boot_file = NULL;
+#if 0
+static uint8_t rockchip_edid[128]; /* EDID storage */
+#endif
+u_int uboot_args[4] = { 0 }; /* filled in by rockchip_start.S (not in bss) */
+
+/* Same things, but for the free (unused by the kernel) memory. */
+
+extern char KERNEL_BASE_phys[];
+extern char _end[];
+
+#if NCOM > 0
+int use_fb_console = false;
+#else
+int use_fb_console = true;
+#endif
+
+/*
+ * Macros to translate between physical and virtual for a subset of the
+ * kernel address space. *Not* for general use.
+ */
+#define KERNEL_BASE_PHYS ((paddr_t)KERNEL_BASE_phys)
+#define ROCKCHIP_CORE0_VOFFSET (ROCKCHIP_CORE0_VBASE - ROCKCHIP_CORE0_BASE)
+#define ROCKCHIP_CORE1_VOFFSET (ROCKCHIP_CORE1_VBASE - ROCKCHIP_CORE1_BASE)
+/* Prototypes */
+
+void consinit(void);
+#ifdef KGDB
+static void kgdb_port_init(void);
+#endif
+
+static void init_clocks(void);
+static void rockchip_device_register(device_t, void *);
+static void rockchip_reset(void);
+
+bs_protos(bs_notimpl);
+
+#if NCOM > 0
+#include <dev/ic/comreg.h>
+#include <dev/ic/comvar.h>
+#endif
+
+/*
+ * Static device mappings. These peripheral registers are mapped at
+ * fixed virtual addresses very early in initarm() so that we can use
+ * them while booting the kernel, and stay at the same address
+ * throughout whole kernel's life time.
+ *
+ * We use this table twice; once with bootstrap page table, and once
+ * with kernel's page table which we build up in initarm().
+ *
+ * Since we map these registers into the bootstrap page table using
+ * pmap_devmap_bootstrap() which calls pmap_map_chunk(), we map
+ * registers segment-aligned and segment-rounded in order to avoid
+ * using the 2nd page tables.
+ */
+
+#define _A(a) ((a) & ~L1_S_OFFSET)
+#define _S(s) (((s) + L1_S_SIZE - 1) & ~(L1_S_SIZE-1))
+
+static const struct pmap_devmap devmap[] = {
+ {
+ .pd_va = _A(ROCKCHIP_CORE0_VBASE),
+ .pd_pa = _A(ROCKCHIP_CORE0_BASE),
+ .pd_size = _S(ROCKCHIP_CORE0_SIZE),
+ .pd_prot = VM_PROT_READ|VM_PROT_WRITE,
+ .pd_cache = PTE_NOCACHE
+ },
+ {
+ .pd_va = _A(ROCKCHIP_CORE1_VBASE),
+ .pd_pa = _A(ROCKCHIP_CORE1_BASE),
+ .pd_size = _S(ROCKCHIP_CORE1_SIZE),
+ .pd_prot = VM_PROT_READ|VM_PROT_WRITE,
+ .pd_cache = PTE_NOCACHE
+ },
+ {0}
+};
+
+#undef _A
+#undef _S
+
+#ifdef DDB
+static void
+rockchip_db_trap(int where)
+{
+ /* NOT YET */
+}
+#endif
+
+void rockchip_putchar(char c);
+void
+rockchip_putchar(char c)
+{
+#if NCOM > 0
+ volatile uint32_t *com0addr = (volatile uint32_t *)CONSADDR_VA;
+ int timo = 150000;
+
+ while ((com0addr[com_lsr] & LSR_TXRDY) == 0) {
+ if (--timo == 0)
+ break;
+ }
+
+ com0addr[com_data] = c;
+
+ while ((com0addr[com_lsr] & LSR_TXRDY) == 0) {
+ if (--timo == 0)
+ break;
+ }
+#endif
+}
+
+/*
+ * u_int initarm(...)
+ *
+ * Initial entry point on startup. This gets called before main() is
+ * entered.
+ * It should be responsible for setting up everything that must be
+ * in place when main is called.
+ * This includes
+ * Taking a copy of the boot configuration structure.
+ * Initialising the physical console so characters can be printed.
+ * Setting up page tables for the kernel
+ * Relocating the kernel to the bottom of physical memory
+ */
+u_int
+initarm(void *arg)
+{
+ psize_t ram_size = 0;
+ char *ptr;
+ *(volatile int *)CONSADDR_VA = 0x40; /* output '@' */
+#if 1
+ rockchip_putchar('d');
+#endif
+
+ /* Heads up ... Setup the CPU / MMU / TLB functions. */
+ if (set_cpufuncs())
+ panic("cpu not recognized!");
+
+curcpu()->ci_data.cpu_cc_freq = 1600000000; /* XXX hack XXX */
+
+ init_clocks();
+
+ /* The console is going to try to map things. Give pmap a devmap. */
+ pmap_devmap_register(devmap);
+ consinit();
+#ifdef CPU_CORTEXA15
+#ifdef MULTIPROCESSOR
+ arm_cpu_max = 1 + __SHIFTOUT(armreg_l2ctrl_read(), L2CTRL_NUMCPU);
+#endif
+#endif
+
+#if NARML2CC > 0
+ /*
+ * Probe the PL310 L2CC
+ */
+ printf("probe the PL310 L2CC\n");
+ const bus_space_handle_t pl310_bh = ROCKCHIP_PL310_BASE
+ + ROCKCHIP_CORE0_VBASE - ROCKCHIP_CORE0_BASE;
+ arml2cc_init(&rockchip_a4x_bs_tag, pl310_bh, 0);
+ rockchip_putchar('l');
+#endif
+
+ printf("\nuboot arg = %#x, %#x, %#x, %#x\n",
+ uboot_args[0], uboot_args[1], uboot_args[2], uboot_args[3]);
+
+
+#ifdef KGDB
+ kgdb_port_init();
+#endif
+
+ cpu_reset_address = rockchip_reset;
+
+#ifdef VERBOSE_INIT_ARM
+ /* Talk to the user */
+ printf("\nNetBSD/evbarm (rockchip) booting ...\n");
+#endif
+
+#ifdef BOOT_ARGS
+ char mi_bootargs[] = BOOT_ARGS;
+ parse_mi_bootargs(mi_bootargs);
+#endif
+
+#ifdef VERBOSE_INIT_ARM
+ printf("initarm: Configuring system ...\n");
+#endif
+
+#if !defined(CPU_CORTEXA8)
+ printf("initarm: cbar=%#x\n", armreg_cbar_read());
+ printf("KERNEL_BASE=0x%x, KERNEL_VM_BASE=0x%x, KERNEL_VM_BASE - KERNEL_BASE=0x%x, KERNEL_BASE_VOFFSET=0x%x\n",
+ KERNEL_BASE, KERNEL_VM_BASE, KERNEL_VM_BASE - KERNEL_BASE, KERNEL_BASE_VOFFSET);
+#endif
+
+#ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
+ if (ram_size > KERNEL_VM_BASE - KERNEL_BASE) {
+ printf("%s: dropping RAM size from %luMB to %uMB\n",
+ __func__, (unsigned long) (ram_size >> 20),
+ (KERNEL_VM_BASE - KERNEL_BASE) >> 20);
+ ram_size = KERNEL_VM_BASE - KERNEL_BASE;
+ }
+#endif
+
+ /*
+ * If MEMSIZE specified less than what we really have, limit ourselves
+ * to that.
+ */
+#ifdef MEMSIZE
+ if (ram_size == 0 || ram_size > (unsigned)MEMSIZE * 1024 * 1024)
+ ram_size = (unsigned)MEMSIZE * 1024 * 1024;
+ printf("ram_size = 0x%x\n", (int)ram_size);
+#else
+ KASSERTMSG(ram_size > 0, "RAM size unknown and MEMSIZE undefined");
+#endif
+
+ /* Fake bootconfig structure for the benefit of pmap.c. */
+ bootconfig.dramblocks = 1;
+ bootconfig.dram[0].address = 0x60000000; /* SDRAM PHY addr */
+ bootconfig.dram[0].pages = ram_size / PAGE_SIZE;
+
+#ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
+ const bool mapallmem_p = true;
+ KASSERT(ram_size <= KERNEL_VM_BASE - KERNEL_BASE);
+#else
+ const bool mapallmem_p = false;
+#endif
+ KASSERT((armreg_pfr1_read() & ARM_PFR1_SEC_MASK) != 0);
+
+ arm32_bootmem_init(bootconfig.dram[0].address, ram_size,
+ KERNEL_BASE_PHYS);
+ arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_LOW, 0, devmap,
+ mapallmem_p);
+
+#ifdef __HAVE_MM_MD_DIRECT_MAPPED_PHYS
+ /* "bootargs" env variable is passed as 4th argument to kernel */
+ if (uboot_args[3] - 0x80000000 < ram_size) {
+ strlcpy(bootargs, (char *)uboot_args[3], sizeof(bootargs));
+ }
+#endif
+ boot_args = bootargs;
+ parse_mi_bootargs(boot_args);
+
+ /* we've a specific device_register routine */
+ evbarm_device_register = rockchip_device_register;
+
+ db_trap_callback = rockchip_db_trap;
+
+ if (get_bootconf_option(boot_args, "console",
+ BOOTOPT_TYPE_STRING, &ptr) && strncmp(ptr, "fb", 2) == 0) {
+ use_fb_console = true;
+ }
+
+ return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
+
+}
+
+static void
+init_clocks(void)
+{
+ /* NOT YET */
+}
+
+#if NCOM > 0
+#ifndef CONSADDR
+#error Specify the address of the console UART with the CONSADDR option.
+#endif
+#ifndef CONSPEED
+#define CONSPEED 115200
+#endif
+#ifndef CONMODE
+#define CONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
+#endif
+
+static const bus_addr_t consaddr = CONSADDR;
+static const int conspeed = CONSPEED;
+static const int conmode = CONMODE;
+#endif
+
+void
+consinit(void)
+{
+#if NCOM > 0
+ bus_space_handle_t bh;
+#endif
+ static int consinit_called = 0;
+
+ if (consinit_called != 0)
+ return;
+
+ consinit_called = 1;
+
+ rockchip_putchar('e');
+
+#if NCOM > 0
+ if (bus_space_map(&rockchip_a4x_bs_tag, consaddr, ROCKCHIP_UART_SIZE, 0, &bh))
+ panic("Serial console can not be mapped.");
+
+ if (comcnattach(&rockchip_a4x_bs_tag, consaddr, conspeed,
+ ROCKCHIP_UART_FREQ, COM_TYPE_NORMAL, conmode))
+ panic("Serial console can not be initialized.");
+
+ bus_space_unmap(&rockchip_a4x_bs_tag, bh, ROCKCHIP_UART_SIZE);
+#endif
+
+
+#if NUKBD > 0
+ ukbd_cnattach(); /* allow USB keyboard to become console */
+#endif
+
+ rockchip_putchar('f');
+ rockchip_putchar('g');
+}
+
+void
+rockchip_reset(void)
+{
+ /* NOT YET */
+}
+
+#ifdef KGDB
+#ifndef KGDB_DEVADDR
+#error Specify the address of the kgdb UART with the KGDB_DEVADDR option.
+#endif
+#ifndef KGDB_DEVRATE
+#define KGDB_DEVRATE 115200
+#endif
+
+#ifndef KGDB_DEVMODE
+#define KGDB_DEVMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
+#endif
+static const vaddr_t comkgdbaddr = KGDB_DEVADDR;
+static const int comkgdbspeed = KGDB_DEVRATE;
+static const int comkgdbmode = KGDB_DEVMODE;
+
+void
+static kgdb_port_init(void)
+{
+ static int kgdbsinit_called = 0;
+
+ if (kgdbsinit_called != 0)
+ return;
+
+ kgdbsinit_called = 1;
+
+ bus_space_handle_t bh;
+ if (bus_space_map(&rockchip_a4x_bs_tag, comkgdbaddr, ROCKCHIP_COM_SIZE, 0, &bh))
+ panic("kgdb port can not be mapped.");
+
+ if (com_kgdb_attach(&rockchip_a4x_bs_tag, comkgdbaddr, comkgdbspeed,
+ ROCKCHIP_COM_FREQ, COM_TYPE_NORMAL, comkgdbmode))
+ panic("KGDB uart can not be initialized.");
+
+ bus_space_unmap(&rockchip_a4x_bs_tag, bh, ROCKCHIP_COM_SIZE);
+}
+#endif
+
+void
+rockchip_device_register(device_t self, void *aux)
+{
+ prop_dictionary_t dict = device_properties(self);
+
+ if (device_is_a(self, "armperiph")
+ && device_is_a(device_parent(self), "mainbus")) {
+ /*
+ * XXX KLUDGE ALERT XXX
+ * The iot mainbus supplies is completely wrong since it scales
+ * addresses by 2. The simpliest remedy is to replace with our
+ * bus space used for the armcore regisers (which armperiph uses).
+ */
+ struct mainbus_attach_args * const mb = aux;
+ mb->mb_iot = &rockchip_bs_tag;
+ return;
+ }
+
+#ifdef CPU_CORTEXA9
+ /*
+ * We need to tell the A9 Global/Watchdog Timer
+ * what frequency it runs at.
+ */
+ if (device_is_a(self, "a9tmr") || device_is_a(self, "a9wdt")) {
+ /*
+ * This clock always runs at (arm_clk div 2) and only goes
+ * to timers that are part of the A9 MP core subsystem.
+ */
+ prop_dictionary_set_uint32(dict, "frequency", 148500000); /* 148.5MHz */
+ return;
+ }
+
+ if (device_is_a(self, "arml2cc")) {
+ prop_dictionary_set_uint32(dict, "offset", 0xffffc000); /* -0x4000 */
+ return;
+ }
+#endif
+}
Index: src/sys/arch/evbarm/rockchip/rockchip_start.S
diff -u /dev/null src/sys/arch/evbarm/rockchip/rockchip_start.S:1.1
--- /dev/null Fri Dec 26 16:53:33 2014
+++ src/sys/arch/evbarm/rockchip/rockchip_start.S Fri Dec 26 16:53:33 2014
@@ -0,0 +1,289 @@
+/*-
+ * Copyright (c) 2014 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Matt Thomas of 3am Software Foundry.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "opt_rockchip.h"
+#include "opt_com.h"
+#include "opt_cpuoptions.h"
+#include "opt_cputypes.h"
+#include "opt_multiprocessor.h"
+#include "opt_arm_debug.h"
+
+#include <arm/asm.h>
+#include <arm/armreg.h>
+#include "assym.h"
+
+#include <arm/rockchip/rockchip_reg.h>
+#include <evbarm/rockchip/platform.h>
+
+RCSID("$NetBSD: rockchip_start.S,v 1.1 2014/12/26 16:53:33 jmcneill Exp $")
+
+#if defined(VERBOSE_INIT_ARM)
+#define XPUTC(n) mov r0, n; bl xputc
+#if KERNEL_BASE_VOFFSET == 0
+#define XPUTC2(n) mov r0, n; bl xputc
+#else
+#define XPUTC2(n) mov r0, n; blx r11
+#endif
+#ifdef __ARMEB__
+#define COM_BSWAP
+#endif
+#define COM_MULT 4
+#define XPUTC_COM 1
+#else
+#define XPUTC(n)
+#define XPUTC2(n)
+#endif
+
+#define INIT_MEMSIZE 128
+#define TEMP_L1_TABLE (KERNEL_BASE - KERNEL_BASE_VOFFSET + INIT_MEMSIZE * L1_S_SIZE - L1_TABLE_SIZE)
+
+#define MD_CPU_HATCH _C_LABEL(a9tmr_init_cpu_clock)
+
+/*
+ * Kernel start routine for CUBIE (Allwinner) boards.
+ * At this point, this code has been loaded into SDRAM
+ * and the MMU maybe on or maybe off.
+ */
+#ifdef KERNEL_BASES_EQUAL
+ .text
+#else
+ .section .start,"ax",%progbits
+#endif
+
+ .global _C_LABEL(rockchip_start)
+_C_LABEL(rockchip_start):
+#ifdef __ARMEB__
+ setend be /* force big endian */
+#endif
+ mov r9, #0
+
+ /* Move into supervisor mode and disable IRQs/FIQs. */
+ cpsid if, #PSR_SVC32_MODE
+#if 0
+ /*
+ * Save any arguments passed to us.
+ */
+ movw r4, #:lower16:uboot_args
+ movt r4, #:upper16:uboot_args
+#if KERNEL_BASE_VOFFSET != 0
+ /*
+ * But since .start is at 0x40000000 and .text is at 0x8000000, we
+ * can't directly use the address that the linker gave us directly.
+ * We have to adjust the address the linker gave us to get the to
+ * the physical address.
+ */
+ sub r4, r4, #KERNEL_BASE_VOFFSET
+#endif
+
+ stmia r4, {r0-r3} // Save the arguments
+#endif
+ /*
+ * Turn on the SMP bit
+ */
+ bl cortex_init
+
+ /*
+ * Set up a preliminary mapping in the MMU to allow us to run
+ * at KERNEL_BASE with caches on.
+ */
+ movw r0, #:lower16:TEMP_L1_TABLE
+ movt r0, #:upper16:TEMP_L1_TABLE
+ movw r1, #:lower16:.Lmmu_init_table
+ movt r1, #:upper16:.Lmmu_init_table
+ bl arm_boot_l1pt_init
+ XPUTC(#68)
+
+ /*
+ * Turn on the MMU, Caches, etc. Return to new enabled address space.
+ */
+ movw r0, #:lower16:TEMP_L1_TABLE
+ movt r0, #:upper16:TEMP_L1_TABLE
+#if KERNEL_BASE_VOFFSET == 0
+ bl arm_cpuinit
+#else
+ /*
+ * After the MMU is on, we can execute in the normal .text segment
+ * so setup the lr to be in .text. Cache the address for xputc
+ * before we go.
+ */
+#if defined(VERBOSE_INIT_ARM)
+ adr r11, xputc @ for XPUTC2
+#endif
+ movw lr, #:lower16:1f
+ movt lr, #:upper16:1f
+ b arm_cpuinit
+ .pushsection .text,"ax",%progbits
+1:
+#endif
+ XPUTC2(#90)
+
+#if defined(MULTIPROCESSOR)
+ // Now spin up the second processors into the same state we are now.
+ XPUTC2(#77)
+ XPUTC2(#80)
+ XPUTC2(#60)
+ // Make sure the cache is flushed out to RAM for the other CPUs
+ bl _C_LABEL(armv7_dcache_wbinv_all)
+ bl a20_mpinit
+ XPUTC2(#62)
+#endif /* MULTIPROCESSOR */
+ XPUTC2(#13)
+ XPUTC2(#10)
+
+ /*
+ * Jump to start in locore.S, which in turn will call initarm and main.
+ */
+ b start
+
+ /* NOTREACHED */
+
+#ifndef KERNEL_BASES_EQUAL
+ .popsection
+#endif
+
+#include <arm/cortex/a9_mpsubr.S>
+
+#if defined(MULTIPROCESSOR)
+#ifndef KERNEL_BASES_EQUAL
+ .pushsection .text,"ax",%progbits
+#endif
+a20_mpinit:
+ mov r4, lr // because we call gtmr_bootdelay
+ movw r5, #:lower16:(ROCKCHIP_CORE_PBASE+ROCKCHIP_CPUCFG_OFFSET)
+ movt r5, #:upper16:(ROCKCHIP_CORE_PBASE+ROCKCHIP_CPUCFG_OFFSET)
+
+ /* Set where the other CPU(s) are going to execute */
+ movw r1, #:lower16:cortex_mpstart
+ movt r1, #:upper16:cortex_mpstart
+ str r1, [r5, #ROCKCHIP_CPUCFG_PRIVATE_REG]
+ dsb
+
+ /* Assert CPU core reset */
+ mov r1, #0
+ str r1, [r5, #ROCKCHIP_CPUCFG_CPU1_RST_CTRL_REG]
+ dsb
+
+ /* Ensure CPU1 reset also invalidates its L1 caches */
+ ldr r1, [r5, #ROCKCHIP_CPUCFG_GENCTRL_REG]
+ bic r1, r1, #(1 << 1)
+ str r1, [r5, #ROCKCHIP_CPUCFG_GENCTRL_REG]
+ dsb
+
+ /* Hold DBGPWRDUP signal low */
+ ldr r1, [r5, #ROCKCHIP_CPUCFG_DBGCTRL1_REG]
+ bic r1, r1, #(1 << 1)
+ str r1, [r5, #ROCKCHIP_CPUCFG_DBGCTRL1_REG]
+ dsb
+
+ /* Ramp up power to CPU1 */
+ movw r1, #0xff
+1: str r1, [r5, #ROCKCHIP_CPUCFG_CPU1_PWRCLAMP_REG]
+ dsb
+ lsrs r1, r1, #1
+ bne 1b
+
+ /* We need to wait (at least) 10ms */
+ mov r0, #0x3b000 // 10.06ms
+ bl _C_LABEL(gtmr_bootdelay)
+
+ /* Clear power-off gating */
+ ldr r1, [r5, #ROCKCHIP_CPUCFG_CPU1_PWROFF_REG]
+ bic r1, r1, #(1 << 1)
+ str r1, [r5, #ROCKCHIP_CPUCFG_CPU1_PWROFF_REG]
+ dsb
+
+ /* Bring CPU1 out of reset */
+ ldr r1, [r5, #ROCKCHIP_CPUCFG_CPU1_RST_CTRL_REG]
+ orr r1, r1, #(ROCKCHIP_CPUCFG_CPU_RST_CTRL_CORE_RESET|ROCKCHIP_CPUCFG_CPU_RST_CTRL_RESET)
+ str r1, [r5, #ROCKCHIP_CPUCFG_CPU1_RST_CTRL_REG]
+ dsb
+
+ /* Reassert DBGPWRDUP signal */
+ ldr r1, [r5, #ROCKCHIP_CPUCFG_DBGCTRL1_REG]
+ orr r1, r1, #(1 << 1)
+ str r1, [r5, #ROCKCHIP_CPUCFG_DBGCTRL1_REG]
+ dsb
+
+ //
+ // Wait up a second for CPU1 to hatch.
+ //
+ movw r6, #:lower16:arm_cpu_hatched
+ movt r6, #:upper16:arm_cpu_hatched
+ mov r5, #200 // 200 x 5ms
+
+1: dmb // memory barrier
+ ldr r0, [r6] // load hatched
+ tst r0, #2 // our bit set yet?
+ bxne r4 // yes, return
+ subs r5, r5, #1 // decrement count
+ bxeq r4 // 0? return
+ mov r0, #0x1d800 // 5.03ms
+ bl _C_LABEL(gtmr_bootdelay)
+ b 1b
+ASEND(a20_mpinit)
+#ifndef KERNEL_BASES_EQUAL
+ .popsection
+#endif
+#endif /* MULTIPROCESSOR */
+
+.Lmmu_init_table:
+ /* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
+ MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
+
+#if KERNEL_BASE_VOFFSET != 0
+ /* Map memory 1:1 VA to PA, write-back cacheable, shareable */
+ MMU_INIT(KERNEL_BASE - KERNEL_BASE_VOFFSET,
+ KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
+#endif
+
+ /* Map ROCKCHIP CORE0 */
+ MMU_INIT(ROCKCHIP_CORE0_VBASE, ROCKCHIP_CORE0_BASE,
+ (ROCKCHIP_CORE0_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
+
+ /* Map ROCKCHIP CORE0 */
+ MMU_INIT(ROCKCHIP_CORE0_BASE, ROCKCHIP_CORE0_BASE,
+ (ROCKCHIP_CORE0_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
+
+ /* Map ROCKCHIP CORE1 (so console will work) */
+ MMU_INIT(ROCKCHIP_CORE1_VBASE, ROCKCHIP_CORE1_BASE,
+ (ROCKCHIP_CORE1_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
+
+ /* Map ROCKCHIP CORE1 (so console will work) */
+ MMU_INIT(ROCKCHIP_CORE1_BASE, ROCKCHIP_CORE1_BASE,
+ (ROCKCHIP_CORE1_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
+ L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
+ /* end of table */
+ MMU_INIT(0, 0, 0, 0)
+
+END(_C_LABEL(rockchip_start))
