Module Name: src
Committed By: jmcneill
Date: Fri Dec 26 19:44:48 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: files.rockchip obio.c obio_com.c
rockchip_dwctwo.c rockchip_reg.h rockchip_var.h
src/sys/arch/evbarm/rockchip: rockchip_machdep.c
Added Files:
src/sys/arch/arm/rockchip: rockchip_board.c
Log Message:
Map all of core0 and core1 space and let drivers use bus_space_subregion
instead of bus_space_map. Fill in rockchip_reset.
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/rockchip/files.rockchip \
src/sys/arch/arm/rockchip/obio.c src/sys/arch/arm/rockchip/obio_com.c \
src/sys/arch/arm/rockchip/rockchip_dwctwo.c \
src/sys/arch/arm/rockchip/rockchip_reg.h \
src/sys/arch/arm/rockchip/rockchip_var.h
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/rockchip/rockchip_board.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/evbarm/rockchip/rockchip_machdep.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/files.rockchip
diff -u src/sys/arch/arm/rockchip/files.rockchip:1.1 src/sys/arch/arm/rockchip/files.rockchip:1.2
--- src/sys/arch/arm/rockchip/files.rockchip:1.1 Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/files.rockchip Fri Dec 26 19:44:48 2014
@@ -1,4 +1,4 @@
-# $NetBSD: files.rockchip,v 1.1 2014/12/26 16:53:33 jmcneill Exp $
+# $NetBSD: files.rockchip,v 1.2 2014/12/26 19:44:48 jmcneill Exp $
#
# Configuration info for Rockchip ARM Peripherals
#
@@ -11,6 +11,7 @@ file arch/arm/arm32/arm32_kvminit.c
file arch/arm/arm32/arm32_reboot.c
file arch/arm/arm32/irq_dispatch.S
+file arch/arm/rockchip/rockchip_board.c
file arch/arm/rockchip/rockchip_space.c obio
#file arch/arm/rockchip/rockchip_a4x_space.c obio
file arch/arm/rockchip/rockchip_dma.c
@@ -25,11 +26,11 @@ file arch/arm/rockchip/obio.c obio
attach com at obio with obiouart
file arch/arm/rockchip/obio_com.c obiouart
-# SDHC
-#attach sdhc at obio with rksdhc
-#file arch/arm/rockchip/rockchip_sdhc.c rksdhc
+# SD/MMC (Synopsys DesignWare)
+attach dwcmmc at obio with rkdwcmmc
+file arch/arm/rockchip/rockchip_dwcmmc.c rkdwcmmc
-# USB OTG (Synopsys DesignWave OTG)
+# USB OTG (Synopsys DesignWare OTG)
attach dwctwo at obio with rkdwctwo
file arch/arm/rockchip/rockchip_dwctwo.c rkdwctwo needs-flag
Index: src/sys/arch/arm/rockchip/obio.c
diff -u src/sys/arch/arm/rockchip/obio.c:1.1 src/sys/arch/arm/rockchip/obio.c:1.2
--- src/sys/arch/arm/rockchip/obio.c:1.1 Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/obio.c Fri Dec 26 19:44:48 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: obio.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+/* $NetBSD: obio.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
/*
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
@@ -36,7 +36,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: obio.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: obio.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -100,14 +100,16 @@ int
obio_print(void *aux, const char *pnp)
{
struct obio_attach_args *obio = aux;
+ bus_addr_t addr = obio->obio_base + obio->obio_offset;
- aprint_normal(": addr 0x%08lx", obio->obio_addr);
- aprint_normal("-0x%08lx", obio->obio_addr + (obio->obio_size - 1));
+ aprint_normal(": addr 0x%08lx", addr);
+ aprint_normal("-0x%08lx", addr + (obio->obio_size - 1));
if (obio->obio_width != OBIOCF_WIDTH_DEFAULT)
aprint_normal(" width %d", obio->obio_width);
if (obio->obio_intr != OBIOCF_INTR_DEFAULT)
aprint_normal(" intr %d", obio->obio_intr);
- aprint_normal(" mult %d", obio->obio_mult);
+ if (obio->obio_mult != OBIOCF_MULT_DEFAULT)
+ aprint_normal(" mult %d", obio->obio_mult);
return UNCONF;
}
@@ -116,21 +118,33 @@ int
obio_search(device_t parent, cfdata_t cf, const int *ldesc, void *aux)
{
struct obio_attach_args obio;
+ bus_addr_t addr = cf->cf_loc[OBIOCF_ADDR];
- obio.obio_addr = cf->cf_loc[OBIOCF_ADDR];
+ if (addr >= ROCKCHIP_CORE0_BASE &&
+ addr < ROCKCHIP_CORE0_BASE + ROCKCHIP_CORE0_SIZE) {
+ obio.obio_base = ROCKCHIP_CORE0_BASE;
+ obio.obio_bsh = rockchip_core0_bsh;
+ } else if (addr >= ROCKCHIP_CORE1_BASE &&
+ addr < ROCKCHIP_CORE1_BASE + ROCKCHIP_CORE1_SIZE) {
+ obio.obio_base = ROCKCHIP_CORE1_BASE;
+ obio.obio_bsh = rockchip_core1_bsh;
+ } else {
+ panic("addr %#llx is not in CORE0 or CORE1 space",
+ (long long unsigned int)addr);
+ }
+ obio.obio_offset = addr - obio.obio_base;
obio.obio_size = cf->cf_loc[OBIOCF_SIZE];
obio.obio_width = cf->cf_loc[OBIOCF_WIDTH];
obio.obio_intr = cf->cf_loc[OBIOCF_INTR];
obio.obio_mult = cf->cf_loc[OBIOCF_MULT];
obio.obio_dmat = &rockchip_bus_dma_tag;
-
switch (cf->cf_loc[OBIOCF_MULT]) {
case 1:
- obio.obio_iot = &rockchip_bs_tag;
+ obio.obio_bst = &rockchip_bs_tag;
break;
case 4:
- obio.obio_iot = &rockchip_a4x_bs_tag;
+ obio.obio_bst = &rockchip_a4x_bs_tag;
break;
default:
panic("Unsupported EMIFS multiplier.");
@@ -160,16 +174,14 @@ void obio_iomux(int offset, int new)
bus_space_tag_t bt = &rockchip_bs_tag;
int old, renew;
- if (bus_space_map(bt, ROCKCHIP_GRF_BASE, ROCKCHIP_GRF_SIZE, 0, &bh))
- panic("GRF can not be mapped.");
+ bus_space_subregion(bt, rockchip_core1_bsh, ROCKCHIP_GRF_OFFSET,
+ ROCKCHIP_GRF_SIZE, &bh);
old = bus_space_read_4(bt, bh, offset);
bus_space_write_4(bt, bh, offset, (old | new | 0xffff0000));
renew = bus_space_read_4(bt, bh, offset);
printf("grf iomux: old %08x, new %08x, renew %08x\n", old, new, renew);
-
- bus_space_unmap(bt, bh, ROCKCHIP_GRF_SIZE);
}
#define GPIO_SWPORTA_DR_OFFSET 0x00
@@ -177,8 +189,8 @@ void obio_iomux(int offset, int new)
void obio_init_gpio(void)
{
- obio_swporta(ROCKCHIP_GPIO0_BASE, GPIO_SWPORTA_DR_OFFSET, __BIT(3));
- obio_swporta(ROCKCHIP_GPIO0_BASE, GPIO_SWPORTA_DD_OFFSET, __BIT(3));
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(3));
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(3));
}
void obio_swporta(int gpio_base, int offset, int new)
@@ -188,14 +200,11 @@ void obio_swporta(int gpio_base, int off
int old, renew;
int gpio_size = 0x100; /* XXX */
- if (bus_space_map(bt, gpio_base, gpio_size, 0, &bh))
- panic("gpio can not be mapped.");
+ bus_space_subregion(bt, rockchip_core1_bsh, gpio_base, gpio_size, &bh);
old = bus_space_read_4(bt, bh, offset);
bus_space_write_4(bt, bh, offset, old | new);
renew = bus_space_read_4(bt, bh, offset);
printf("gpio: 0x%08x 0x%08x -> 0x%08x\n", gpio_base + offset, old, renew);
-
- bus_space_unmap(bt, bh, gpio_size);
}
Index: src/sys/arch/arm/rockchip/obio_com.c
diff -u src/sys/arch/arm/rockchip/obio_com.c:1.1 src/sys/arch/arm/rockchip/obio_com.c:1.2
--- src/sys/arch/arm/rockchip/obio_com.c:1.1 Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/obio_com.c Fri Dec 26 19:44:48 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: obio_com.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+/* $NetBSD: obio_com.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
/* based on omap/obio_com.c */
@@ -41,7 +41,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: obio_com.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: obio_com.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $");
#include "opt_rockchip.h"
/*#include "opt_com.h"*/
@@ -77,10 +77,24 @@ static int
obiouart_match(device_t parent, cfdata_t cf, void *aux)
{
struct obio_attach_args *obio = aux;
- bus_space_handle_t bh;
- int rv;
- if (obio->obio_addr == OBIOCF_ADDR_DEFAULT)
+ bus_space_handle_t bsh;
+ bus_addr_t ioaddr;
+
+ switch (obio->obio_base) {
+ case ROCKCHIP_CORE0_BASE:
+ KASSERT(obio->obio_offset == ROCKCHIP_UART0_OFFSET ||
+ obio->obio_offset == ROCKCHIP_UART1_OFFSET);
+ break;
+ case ROCKCHIP_CORE1_BASE:
+ KASSERT(obio->obio_offset == ROCKCHIP_UART2_OFFSET ||
+ obio->obio_offset == ROCKCHIP_UART3_OFFSET);
+ break;
+ default:
panic("obiouart must have addr specified in config.");
+ }
+
+ ioaddr = obio->obio_base + obio->obio_offset;
+
#if 0
/*
* XXX this should be ifdefed on a board-dependent switch
@@ -93,18 +107,13 @@ obiouart_match(device_t parent, cfdata_t
if (obio->obio_size == OBIOCF_SIZE_DEFAULT)
obio->obio_size = ROCKCHIP_UART_SIZE;
- if (com_is_console(obio->obio_iot, obio->obio_addr, NULL))
+ if (com_is_console(obio->obio_bst, ioaddr, NULL))
return 1;
- if (bus_space_map(obio->obio_iot, obio->obio_addr, obio->obio_size,
- 0, &bh))
- return 1;
-
- rv = comprobe1(obio->obio_iot, bh);
+ bus_space_subregion(obio->obio_bst, obio->obio_bsh, obio->obio_size, 0,
+ &bsh);
- bus_space_unmap(obio->obio_iot, bh, obio->obio_size);
-
- return rv;
+ return comprobe1(obio->obio_bst, bsh);
}
static void
@@ -113,24 +122,23 @@ obiouart_attach(device_t parent, device_
struct com_obio_softc *osc = device_private(self);
struct com_softc *sc = &osc->sc_sc;
struct obio_attach_args *obio = aux;
- bus_space_tag_t iot;
- bus_space_handle_t ioh = 0;
+ bus_space_tag_t bst;
+ bus_space_handle_t bsh = 0;
bus_addr_t iobase;
-
sc->sc_dev = self;
- iot = obio->obio_iot;
- iobase = obio->obio_addr;
+ bst = obio->obio_bst;
+ iobase = obio->obio_base + obio->obio_offset;
sc->sc_frequency = ROCKCHIP_UART_FREQ;
sc->sc_type = COM_TYPE_NORMAL;
- if (com_is_console(iot, iobase, &ioh) == 0 &&
- bus_space_map(iot, iobase, obio->obio_size, 0, &ioh)) {
+ if (com_is_console(bst, iobase, &bsh) == 0 &&
+ bus_space_subregion(bst, obio->obio_bsh, obio->obio_size, 0, &bsh)) {
panic(": can't map registers\n");
return;
}
- COM_INIT_REGS(sc->sc_regs, iot, ioh, iobase);
+ COM_INIT_REGS(sc->sc_regs, bst, bsh, iobase);
com_attach_subr(sc);
aprint_naive("\n");
Index: src/sys/arch/arm/rockchip/rockchip_dwctwo.c
diff -u src/sys/arch/arm/rockchip/rockchip_dwctwo.c:1.1 src/sys/arch/arm/rockchip/rockchip_dwctwo.c:1.2
--- src/sys/arch/arm/rockchip/rockchip_dwctwo.c:1.1 Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/rockchip_dwctwo.c Fri Dec 26 19:44:48 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_dwctwo.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+/* $NetBSD: rockchip_dwctwo.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
@@ -30,7 +30,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rockchip_dwctwo.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rockchip_dwctwo.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $");
#include <sys/param.h>
#include <sys/systm.h>
@@ -112,21 +112,15 @@ rkdwc2_attach(device_t parent, device_t
{
struct rkdwc2_softc *sc = device_private(self);
struct obio_attach_args *obio = aux;
- int error;
sc->sc_dwc2.sc_dev = self;
- sc->sc_dwc2.sc_iot = obio->obio_iot;
+ sc->sc_dwc2.sc_iot = obio->obio_bst;
sc->sc_dwc2.sc_bus.dmatag = obio->obio_dmat;
sc->sc_dwc2.sc_params = &rkdwc2_params;
- error = bus_space_map(obio->obio_iot, obio->obio_addr, obio->obio_size, 0,
- &sc->sc_dwc2.sc_ioh);
- if (error) {
- aprint_error_dev(self,
- "can't map registers for %s: %d\n", obio->obio_name, error);
- return;
- }
+ bus_space_subregion(obio->obio_bst, obio->obio_bsh, obio->obio_offset,
+ obio->obio_size, &sc->sc_dwc2.sc_ioh);
aprint_naive(": USB controller\n");
aprint_normal(": USB controller\n");
@@ -151,7 +145,6 @@ fail:
intr_disestablish(sc->sc_ih);
sc->sc_ih = NULL;
}
- bus_space_unmap(sc->sc_dwc2.sc_iot, sc->sc_dwc2.sc_ioh, obio->obio_size);
}
static void
Index: src/sys/arch/arm/rockchip/rockchip_reg.h
diff -u src/sys/arch/arm/rockchip/rockchip_reg.h:1.1 src/sys/arch/arm/rockchip/rockchip_reg.h:1.2
--- src/sys/arch/arm/rockchip/rockchip_reg.h:1.1 Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/rockchip_reg.h Fri Dec 26 19:44:48 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_reg.h,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+/* $NetBSD: rockchip_reg.h,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -42,43 +42,46 @@
#define ROCKCHIP_CORE0_VBASE 0xFEA00000
#define ROCKCHIP_CORE0_SIZE 0x00300000
-#define ROCKCHIP_OTG_BASE 0x10180000
+/* CORE0 */
+#define ROCKCHIP_OTG_OFFSET 0x00180000
#define ROCKCHIP_OTG_SIZE 0x40000
-#define ROCKCHIP_USB_BASE 0x101C0000
+#define ROCKCHIP_USB_OFFSET 0x001C0000
#define ROCKCHIP_USB_SIZE 0x40000
-#define ROCKCHIP_UART0_BASE 0x10124000
+#define ROCKCHIP_UART0_OFFSET 0x00124000
#define ROCKCHIP_UART0_SIZE 0x400
-#define ROCKCHIP_UART1_BASE 0x10126000
+#define ROCKCHIP_UART1_OFFSET 0x00126000
#define ROCKCHIP_UART1_SIZE 0x400
-#define ROCKCHIP_PL310_BASE 0x10138000
+#define ROCKCHIP_PL310_OFFSET 0x00138000
#define ROCKCHIP_PL310_SIZE 0x1000
-#define ROCKCHIP_GICC_BASE 0x1013C100
+#define ROCKCHIP_GICC_OFFSET 0x0013C100
#define ROCKCHIP_GICC_SIZE 0x100
-#define ROCKCHIP_A9TMR_BASE 0x1013C200
+#define ROCKCHIP_A9TMR_OFFSET 0x0013C200
#define ROCKCHIP_A9TMR_SIZE 0x100
-#define ROCKCHIP_A9WDT_BASE 0x1013C600
+#define ROCKCHIP_A9WDT_OFFSET 0x0013C600
#define ROCKCHIP_A9WDT_SIZE 0x20
-#define ROCKCHIP_GICD_BASE 0x1013D000
+#define ROCKCHIP_GICD_OFFSET 0x0013D000
#define ROCKCHIP_GICD_SIZE 0x1000
#define ROCKCHIP_CORE1_BASE 0x20000000
#define ROCKCHIP_CORE1_VBASE 0xFED00000
#define ROCKCHIP_CORE1_SIZE 0x00100000
-#define ROCKCHIP_GRF_BASE 0x20008000
+/* CORE1 */
+#define ROCKCHIP_CRU_OFFSET 0x00000000
+#define ROCKCHIP_CRU_SIZE 0x4000
+#define ROCKCHIP_GRF_OFFSET 0x00008000
#define ROCKCHIP_GRF_SIZE 0x2000
-
-#define ROCKCHIP_UART2_BASE 0x20064000
+#define ROCKCHIP_UART2_OFFSET 0x00064000
#define ROCKCHIP_UART2_SIZE 0x400
-#define ROCKCHIP_UART3_BASE 0x20068000
+#define ROCKCHIP_UART3_OFFSET 0x00068000
#define ROCKCHIP_UART3_SIZE 0x400
-#define ROCKCHIP_GPIO0_BASE 0x2000A000
+#define ROCKCHIP_GPIO0_OFFSET 0x0000A000
#define ROCKCHIP_GPIO0_SIZE 0x100
-#define ROCKCHIP_GPIO1_BASE 0x2003C000
+#define ROCKCHIP_GPIO1_OFFSET 0x0003C000
#define ROCKCHIP_GPIO1_SIZE 0x100
-#define ROCKCHIP_GPIO2_BASE 0x2003E000
+#define ROCKCHIP_GPIO2_OFFSET 0x0003E000
#define ROCKCHIP_GPIO2_SIZE 0x100
-#define ROCKCHIP_GPIO3_BASE 0x20080000
+#define ROCKCHIP_GPIO3_OFFSET 0x00080000
#define ROCKCHIP_GPIO3_SIZE 0x100
#endif /* _ARM_ROCKCHIP_ROCKCHIP_REG_H_ */
Index: src/sys/arch/arm/rockchip/rockchip_var.h
diff -u src/sys/arch/arm/rockchip/rockchip_var.h:1.1 src/sys/arch/arm/rockchip/rockchip_var.h:1.2
--- src/sys/arch/arm/rockchip/rockchip_var.h:1.1 Fri Dec 26 16:53:33 2014
+++ src/sys/arch/arm/rockchip/rockchip_var.h Fri Dec 26 19:44:48 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_var.h,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+/* $NetBSD: rockchip_var.h,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -36,8 +36,10 @@
#include <sys/bus.h>
struct obio_attach_args {
- bus_space_tag_t obio_iot; /* bus space tag */
- bus_addr_t obio_addr; /* address of device */
+ bus_space_tag_t obio_bst; /* bus space tag */
+ bus_space_handle_t obio_bsh; /* bus space handle */
+ bus_addr_t obio_base; /* base address of handle */
+ bus_addr_t obio_offset; /* address of device */
bus_size_t obio_size; /* size of device */
int obio_intr; /* irq */
int obio_width; /* bus width */
@@ -49,5 +51,9 @@ struct obio_attach_args {
extern struct bus_space rockchip_bs_tag;
extern struct bus_space rockchip_a4x_bs_tag;
extern struct arm32_bus_dma_tag rockchip_bus_dma_tag;
+extern bus_space_handle_t rockchip_core0_bsh;
+extern bus_space_handle_t rockchip_core1_bsh;
+
+void rockchip_bootstrap(void);
#endif /* _ARM_ROCKCHIP_ROCKCHIP_VAR_H_ */
Index: src/sys/arch/evbarm/rockchip/rockchip_machdep.c
diff -u src/sys/arch/evbarm/rockchip/rockchip_machdep.c:1.1 src/sys/arch/evbarm/rockchip/rockchip_machdep.c:1.2
--- src/sys/arch/evbarm/rockchip/rockchip_machdep.c:1.1 Fri Dec 26 16:53:33 2014
+++ src/sys/arch/evbarm/rockchip/rockchip_machdep.c Fri Dec 26 19:44:48 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_machdep.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $ */
+/* $NetBSD: rockchip_machdep.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
/*
* Machine dependent functions for kernel setup for TI OSK5912 board.
@@ -125,7 +125,7 @@
*/
#include <sys/cdefs.h>
-__KERNEL_RCSID(0, "$NetBSD: rockchip_machdep.c,v 1.1 2014/12/26 16:53:33 jmcneill Exp $");
+__KERNEL_RCSID(0, "$NetBSD: rockchip_machdep.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $");
#include "opt_machdep.h"
#include "opt_ddb.h"
@@ -181,6 +181,7 @@ __KERNEL_RCSID(0, "$NetBSD: rockchip_mac
#include <dev/ic/ns16550reg.h>
#include <dev/ic/comreg.h>
+#include <arm/rockchip/rockchip_reg.h>
#include <arm/rockchip/rockchip_var.h>
#ifdef CPU_CORTEXA9
@@ -340,6 +341,9 @@ initarm(void *arg)
rockchip_putchar('d');
#endif
+ pmap_devmap_register(devmap);
+ rockchip_bootstrap();
+
/* Heads up ... Setup the CPU / MMU / TLB functions. */
if (set_cpufuncs())
panic("cpu not recognized!");
@@ -348,8 +352,6 @@ curcpu()->ci_data.cpu_cc_freq = 16000000
init_clocks();
- /* The console is going to try to map things. Give pmap a devmap. */
- pmap_devmap_register(devmap);
consinit();
#ifdef CPU_CORTEXA15
#ifdef MULTIPROCESSOR
@@ -362,8 +364,8 @@ curcpu()->ci_data.cpu_cc_freq = 16000000
* Probe the PL310 L2CC
*/
printf("probe the PL310 L2CC\n");
- const bus_space_handle_t pl310_bh = ROCKCHIP_PL310_BASE
- + ROCKCHIP_CORE0_VBASE - ROCKCHIP_CORE0_BASE;
+ const bus_space_handle_t pl310_bh =
+ ROCKCHIP_CORE0_VBASE + ROCKCHIP_PL310_OFFSET;
arml2cc_init(&rockchip_a4x_bs_tag, pl310_bh, 0);
rockchip_putchar('l');
#endif
@@ -520,7 +522,13 @@ consinit(void)
void
rockchip_reset(void)
{
- /* NOT YET */
+ bus_space_tag_t bst = &rockchip_bs_tag;
+ bus_space_handle_t bsh;
+
+ bus_space_subregion(bst, rockchip_core1_bsh,
+ ROCKCHIP_CRU_OFFSET, ROCKCHIP_CRU_SIZE, &bsh);
+
+ bus_space_write_4(bst, bsh, 0x100, 0xfdb9);
}
#ifdef KGDB
Added files:
Index: src/sys/arch/arm/rockchip/rockchip_board.c
diff -u /dev/null src/sys/arch/arm/rockchip/rockchip_board.c:1.1
--- /dev/null Fri Dec 26 19:44:48 2014
+++ src/sys/arch/arm/rockchip/rockchip_board.c Fri Dec 26 19:44:48 2014
@@ -0,0 +1,57 @@
+/* $NetBSD: rockchip_board.c,v 1.1 2014/12/26 19:44:48 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2014 Jared D. McNeill <[email protected]>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0, "$NetBSD: rockchip_board.c,v 1.1 2014/12/26 19:44:48 jmcneill Exp $");
+
+#include <sys/param.h>
+#include <sys/bus.h>
+#include <sys/cpu.h>
+#include <sys/device.h>
+
+#include <arm/rockchip/rockchip_reg.h>
+#include <arm/rockchip/rockchip_var.h>
+
+bus_space_handle_t rockchip_core0_bsh;
+bus_space_handle_t rockchip_core1_bsh;
+
+void
+rockchip_bootstrap(void)
+{
+ int error;
+
+ error = bus_space_map(&rockchip_bs_tag, ROCKCHIP_CORE0_BASE,
+ ROCKCHIP_CORE0_SIZE, 0, &rockchip_core0_bsh);
+ if (error)
+ panic("%s: failed to map CORE0 registers: %d", __func__, error);
+
+ error = bus_space_map(&rockchip_bs_tag, ROCKCHIP_CORE1_BASE,
+ ROCKCHIP_CORE1_SIZE, 0, &rockchip_core1_bsh);
+ if (error)
+ panic("%s: failed to map CORE1 registers: %d", __func__, error);
+}
