> Date: Tue, 10 Oct 2023 20:49:46 +0200
> From: Stefan Sperling <s...@stsp.name>
>
> On Tue, Oct 10, 2023 at 08:41:37PM +0200, Mark Kettenis wrote:
> > So the GMAC_VERSION #define is simply wrong. We should commit the
> > diff attached and drop the sc_core stuff you added below.
>
> That means all our supported chips are GMAC4 and later? Good to know.
Yes, earlier generations are handled by dwge(4).
> > > + switch (PCI_PRODUCT(pa->pa_id)) {
> > > + case PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G:
> > > + sc->sc_phy_mode = DWQE_PHY_MODE_RGMII;
> >
> > This suggests that the PHY must be programmed to disable its internal
> > delays. Our eephy(4) driver doesn't do this. That may explain the
> > poor performance. See how MIIF_SETDELAY, MIIF_RXID and MIIF_TXID are
> > used in rgephy(4).
> >
> > Anyway, that is a different driver, so a separate diff that can go in
> > after this one.
>
> Thanks for the hint. I will take a look.
>
> > > + sc->sc_txfifo_size = 4096 * 8;
> > > + sc->sc_rxfifo_size = 4096 * 8;
> >
> > Makes more sense to simply use 32768 here. Intel's data sheet says 32KB.
>
> I will fix this and send a follow-up version soon.
>
> OK for your diff. Please put it in and I'll rebase on top.
done
> > Index: dev/ic/dwqereg.h
> > ===================================================================
> > RCS file: /cvs/src/sys/dev/ic/dwqereg.h,v
> > retrieving revision 1.2
> > diff -u -p -r1.2 dwqereg.h
> > --- dev/ic/dwqereg.h 16 Feb 2023 14:43:53 -0000 1.2
> > +++ dev/ic/dwqereg.h 10 Oct 2023 18:40:19 -0000
> > @@ -39,8 +39,6 @@
> > #define GMAC_MAC_PACKET_FILTER_PR (1 << 0)
> > #define GMAC_MAC_HASH_TAB_REG0 0x0010
> > #define GMAC_MAC_HASH_TAB_REG1 0x0014
> > -#define GMAC_VERSION 0x0020
> > -#define GMAC_VERSION_SNPS_MASK 0xff
> > #define GMAC_INT_MASK 0x003c
> > #define GMAC_INT_MASK_LPIIM (1 << 10)
> > #define GMAC_INT_MASK_PIM (1 << 3)
> > @@ -60,6 +58,8 @@
> > #define GMAC_INT_STATUS 0x00b0
> > #define GMAC_INT_EN 0x00b4
> > #define GMAC_MAC_1US_TIC_CTR 0x00dc
> > +#define GMAC_VERSION 0x0110
> > +#define GMAC_VERSION_SNPS_MASK 0xff
> > #define GMAC_MAC_HW_FEATURE(x) (0x011c + (x) * 0x4)
> > #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) (((x) >> 6) & 0x1f)
> > #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) (((x) >> 0) & 0x3f)
> >
> >
>
