On Wed, Oct 11, 2023 at 02:05:52PM +0200, Stefan Sperling wrote:
> Anyway, here is an eephy(4) diff to enable/disable delays on the 88E1512.
That diff wasn't quite right. The register offset should be 0x21,
and Linux configures delays every time after link auto-negotiation.
I am still unsure if this change really makes sense, and I cannot
easily verify it as it makes no apparent difference to dwqe(4).
Maybe this change should wait until we really need it?
-----------------------------------------------
add support for Tx/Rx delay settings on 881E512 to eephy(4)
diff 0292379527460b61efdf8c49732814a6faa13cc0
1b3f658f3c2db79931a12fb835f5c11f8e7b170c
commit - 0292379527460b61efdf8c49732814a6faa13cc0
commit + 1b3f658f3c2db79931a12fb835f5c11f8e7b170c
blob - e33abe384313e9301fb6c3292c05ce577ffc890e
blob + c4e39265405869cc631da7120e6c8b501c59aa15
--- sys/dev/mii/eephy.c
+++ sys/dev/mii/eephy.c
@@ -303,6 +303,11 @@ eephy_service(struct mii_softc *sc, struct mii_data *m
{
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
int bmcr;
+ /*
+ * If autonegotiation is not enabled, we need a
+ * software reset for the settings to take effect.
+ */
+ int sw_reset = (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO);
if ((sc->mii_dev.dv_flags & DVF_ACTIVE) == 0)
return (ENXIO);
@@ -335,11 +340,24 @@ eephy_service(struct mii_softc *sc, struct mii_data *m
mii_phy_setmedia(sc);
- /*
- * If autonegotiation is not enabled, we need a
- * software reset for the settings to take effect.
- */
- if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
+ if (sc->mii_model == MII_MODEL_MARVELL_E1512 &&
+ (sc->mii_flags & MIIF_SETDELAY)) {
+ int page, reg;
+ printf("%s: configuring Rx/Tx delay\n", __func__);
+ page = PHY_READ(sc, E1000_EADR);
+ PHY_WRITE(sc, E1000_EADR, 2);
+ reg = PHY_READ(sc, E1000_MSCR2);
+ reg &= ~E1000_MSCR2_DELAY_MASK;
+ if (sc->mii_flags & MIIF_RXID)
+ reg |= E1000_MSCR2_RXDELAY;
+ if (sc->mii_flags & MIIF_TXID)
+ reg |= E1000_MSCR2_TXDELAY;
+ PHY_WRITE(sc, E1000_MSCR2, reg);
+ PHY_WRITE(sc, E1000_EADR, page);
+ sw_reset = 1;
+ }
+
+ if (sw_reset) {
bmcr = PHY_READ(sc, E1000_CR);
PHY_WRITE(sc, E1000_CR, bmcr | E1000_CR_RESET);
}
blob - 59c6c5678987cecde898f44c77b6046a9b7b672f
blob + 41ec501cca74c9a719213c9db1c1bc23ffc31047
--- sys/dev/mii/eephyreg.h
+++ sys/dev/mii/eephyreg.h
@@ -331,3 +331,10 @@
#define E1000_GCR1_RESET 0x8000
#define E1000_GCR1_MODE_MASK 0x0007
#define E1000_GCR1_MODE_SGMII 0x0001
+
+/* The following register is found only on the 88E151x Alaska PHY */
+/* Page 2 */
+#define E1000_MSCR2 0x21 /* MAC-Specific Control Register 2 */
+#define E1000_MSCR2_RXDELAY 0x20
+#define E1000_MSCR2_TXDELAY 0x10
+#define E1000_MSCR2_DELAY_MASK 0x30
