On Tue, Oct 10, 2023 at 09:06:59PM +0200, Mark Kettenis wrote:
> > OK for your diff. Please put it in and I'll rebase on top.
>
> done
Thanks. Here is a rebased version. Re-tested with the same results.
diff refs/heads/master refs/heads/dwqe
commit - 8af2f04850cda85ea291bfaddc0e4d58c40f2935
commit + 539534a1060039a11b4c3faca5385beb016c34de
blob - c6094ca5a57d964784f56124b8d923393b1abb66
blob + cf64e8ff2018fb0ee1e7e59b29b2bc2dd281aa99
--- sys/arch/amd64/conf/GENERIC
+++ sys/arch/amd64/conf/GENERIC
@@ -556,6 +556,7 @@ lii* at pci? # Attansic L2
Ethernet
jme* at pci? # JMicron JMC250/JMC260 Ethernet
bnxt* at pci? # Broadcom BCM573xx, BCM574xx
ixl* at pci? # Intel Ethernet 700 Series
+dwqe* at pci? # Intel Elkhart Lake Ethernet
mcx* at pci? # Mellanox ConnectX-4
iavf* at pci? # Intel Ethernet Adaptive VF
aq* at pci? # Aquantia aQtion Ethernet
blob - 7d260ef46054d6566ef2f81f6cf96dc8de5a5893
blob + 3d01c4f2665c86b8fe4cbb18379afaccf8ca65ac
--- sys/dev/ic/dwqe.c
+++ sys/dev/ic/dwqe.c
@@ -705,7 +705,7 @@ dwqe_up(struct dwqe_softc *sc)
{
struct ifnet *ifp = &sc->sc_ac.ac_if;
struct dwqe_buf *txb, *rxb;
- uint32_t mode, reg, tqs, rqs;
+ uint32_t mode, reg, fifosz, tqs, rqs;
int i;
/* Allocate Tx descriptor ring. */
@@ -793,9 +793,21 @@ dwqe_up(struct dwqe_softc *sc)
mode |= GMAC_MTL_CHAN_RX_OP_MODE_RSF;
}
mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK;
- rqs = (128 << GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1]) /
- 256) - 1;
- mode |= rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT;
+ if (sc->sc_rxfifo_size)
+ fifosz = sc->sc_rxfifo_size;
+ else
+ fifosz = (128 <<
+ GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(sc->sc_hw_feature[1]));
+ rqs = fifosz / 256 - 1;
+ mode |= (rqs << GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT) &
+ GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK;
+ if (fifosz >= 4096) {
+ mode |= GMAC_MTL_CHAN_RX_OP_MODE_EHFC;
+ mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RFD_MASK;
+ mode |= 0x3 << GMAC_MTL_CHAN_RX_OP_MODE_RFD_SHIFT;
+ mode &= ~GMAC_MTL_CHAN_RX_OP_MODE_RFA_MASK;
+ mode |= 0x1 << GMAC_MTL_CHAN_RX_OP_MODE_RFA_SHIFT;
+ }
dwqe_write(sc, GMAC_MTL_CHAN_RX_OP_MODE(0), mode);
mode = dwqe_read(sc, GMAC_MTL_CHAN_TX_OP_MODE(0));
@@ -809,9 +821,14 @@ dwqe_up(struct dwqe_softc *sc)
mode &= ~GMAC_MTL_CHAN_TX_OP_MODE_TXQEN_MASK;
mode |= GMAC_MTL_CHAN_TX_OP_MODE_TXQEN;
mode &= ~GMAC_MTL_CHAN_TX_OP_MODE_TQS_MASK;
- tqs = (128 << GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(sc->sc_hw_feature[1]) /
- 256) - 1;
- mode |= tqs << GMAC_MTL_CHAN_TX_OP_MODE_TQS_SHIFT;
+ if (sc->sc_txfifo_size)
+ fifosz = sc->sc_txfifo_size;
+ else
+ fifosz = (128 <<
+ GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(sc->sc_hw_feature[1]));
+ tqs = (fifosz / 256) - 1;
+ mode |= (tqs << GMAC_MTL_CHAN_TX_OP_MODE_TQS_SHIFT) &
+ GMAC_MTL_CHAN_TX_OP_MODE_TQS_MASK;
dwqe_write(sc, GMAC_MTL_CHAN_TX_OP_MODE(0), mode);
reg = dwqe_read(sc, GMAC_QX_TX_FLOW_CTRL(0));
blob - 68d698a50beef00f002d986d7d24f8984c3efe0c
blob + d5ba09b005c469eec48b17dcbda6c76f277380e7
--- sys/dev/ic/dwqevar.h
+++ sys/dev/ic/dwqevar.h
@@ -97,6 +97,8 @@ struct dwqe_softc {
int sc_pbl;
int sc_txpbl;
int sc_rxpbl;
+ int sc_txfifo_size;
+ int sc_rxfifo_size;
int sc_axi_config;
int sc_lpi_en;
int sc_xit_frm;
blob - 101ed502e76987c27878712b4921cc49f7eb7f59
blob + 6868eb3591995804dbc332308c9d9629f73c269f
--- sys/dev/pci/files.pci
+++ sys/dev/pci/files.pci
@@ -363,6 +363,10 @@ device ixl: ether, ifnet, ifmedia, intrmap, stoeplitz
attach ixl at pci
file dev/pci/if_ixl.c ixl
+# Intel Elkhart Lake Ethernet
+attach dwqe at pci with dwqe_pci
+file dev/pci/if_dwqe_pci.c dwqe_pci
+
# Neterion Xframe 10 Gigabit ethernet
device xge: ether, ifnet, ifmedia
attach xge at pci
blob - /dev/null
blob + d157f116c025d882f1ec8df84b4c3deca3ca340f (mode 644)
--- /dev/null
+++ sys/dev/pci/if_dwqe_pci.c
@@ -0,0 +1,154 @@
+/* $OpenBSD$ */
+
+/*
+ * Copyright (c) 2023 Stefan Sperling <[email protected]>
+ *
+ * Permission to use, copy, modify, and distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * Driver for the Intel Elkhart Lake ethernet controller.
+ */
+
+#include <sys/param.h>
+#include <sys/conf.h>
+#include <sys/systm.h>
+#include <sys/device.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/mbuf.h>
+#include <sys/queue.h>
+#include <sys/socket.h>
+#include <sys/sockio.h>
+#include <sys/timeout.h>
+#include <sys/task.h>
+
+#include <dev/pci/pcireg.h>
+#include <dev/pci/pcivar.h>
+#include <dev/pci/pcidevs.h>
+
+#if NBPFILTER > 0
+#include <net/bpf.h>
+#endif
+#include <net/if.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <dev/ic/dwqereg.h>
+#include <dev/ic/dwqevar.h>
+
+static const struct pci_matchid dwqe_pci_devices[] = {
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G },
+#if 0
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_1G },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE0_SGMII_2G },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_RGMII_1G },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_1G },
+ { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EHL_PSE1_SGMII_2G },
+#endif
+};
+
+struct dwqe_pci_softc {
+ struct dwqe_softc sc_sc;
+ pci_chipset_tag_t sc_pct;
+ pcitag_t sc_pcitag;
+ bus_size_t sc_mapsize;
+};
+
+int
+dwqe_pci_match(struct device *parent, void *cfdata, void *aux)
+{
+ struct pci_attach_args *pa = aux;
+ return pci_matchbyid(pa, dwqe_pci_devices, nitems(dwqe_pci_devices));
+}
+
+void
+dwqe_pci_attach(struct device *parent, struct device *self, void *aux)
+{
+ struct pci_attach_args *pa = aux;
+ struct dwqe_pci_softc *psc = (void *)self;
+ struct dwqe_softc *sc = &psc->sc_sc;
+ pci_intr_handle_t ih;
+ pcireg_t memtype;
+ int err;
+ const char *intrstr;
+
+ psc->sc_pct = pa->pa_pc;
+ psc->sc_pcitag = pa->pa_tag;
+
+ sc->sc_dmat = pa->pa_dmat;
+
+ memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, PCI_MAPREG_START);
+ err = pci_mapreg_map(pa, PCI_MAPREG_START, memtype, 0,
+ &sc->sc_iot, &sc->sc_ioh, NULL, &psc->sc_mapsize, 0);
+ if (err) {
+ printf("%s: can't map mem space\n", DEVNAME(sc));
+ return;
+ }
+
+ if (pci_intr_map_msi(pa, &ih) && pci_intr_map(pa, &ih)) {
+ printf("%s: can't map interrupt\n", DEVNAME(sc));
+ return;
+ }
+
+ intrstr = pci_intr_string(psc->sc_pct, ih);
+ sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET | IPL_MPSAFE,
+ dwqe_intr, psc, sc->sc_dev.dv_xname);
+ if (sc->sc_ih == NULL) {
+ printf(": can't establish interrupt");
+ if (intrstr != NULL)
+ printf(" at %s", intrstr);
+ printf("\n");
+ return;
+ }
+
+ switch (PCI_PRODUCT(pa->pa_id)) {
+ case PCI_PRODUCT_INTEL_EHL_PSE0_RGMII_1G:
+ sc->sc_phy_mode = DWQE_PHY_MODE_RGMII;
+ sc->sc_clk = GMAC_MAC_MDIO_ADDR_CR_250_300;
+ sc->sc_clkrate = 200000000;
+ break;
+ default:
+ sc->sc_phy_mode = DWQE_PHY_MODE_UNKNOWN;
+ break;
+ }
+
+ sc->sc_phyloc = MII_PHY_ANY;
+ sc->sc_8xpbl = 1;
+ sc->sc_txpbl = 32;
+ sc->sc_rxpbl = 32;
+ sc->sc_txfifo_size = 32768;
+ sc->sc_rxfifo_size = 32768;
+
+ sc->sc_axi_config = 1;
+ sc->sc_wr_osr_lmt = 1;
+ sc->sc_rd_osr_lmt = 1;
+ sc->sc_blen[0] = 4;
+ sc->sc_blen[1] = 8;
+ sc->sc_blen[2] = 16;
+
+ dwqe_lladdr_read(sc, sc->sc_lladdr);
+
+ dwqe_reset(sc);
+ dwqe_attach(sc);
+}
+
+const struct cfattach dwqe_pci_ca = {
+ sizeof(struct dwqe_softc), dwqe_pci_match, dwqe_pci_attach
+};
