On Wed, Oct 11, 2023 at 10:27:24AM +0200, Stefan Sperling wrote:
> On Tue, Oct 10, 2023 at 09:06:59PM +0200, Mark Kettenis wrote:
> > > OK for your diff. Please put it in and I'll rebase on top.
> >
> > done
>
> Thanks. Here is a rebased version. Re-tested with the same results.
Turns out I made a mistake when setting up the PHY type because I
misunderstood the Linux driver code.
The phy mode needs to be: sc->sc_phy_mode = DWQE_PHY_MODE_RGMII_ID;
Which means Tx/Rx delays must be enabled (which they are by default).
Anyway, here is an eephy(4) diff to enable/disable delays on the 88E1512.
We might need this eventually in any case.
See Table 110 in the Alaska 88E1510/88E1518/88E1512/88E1514 datasheet
from January 6 2022, page 106/107.
diff /usr/src
commit - 08f2ab0930d2d7a77214a2b9b2623266a5f343ac
path + /usr/src
blob - e33abe384313e9301fb6c3292c05ce577ffc890e
file + sys/dev/mii/eephy.c
--- sys/dev/mii/eephy.c
+++ sys/dev/mii/eephy.c
@@ -200,6 +200,20 @@ eephy_attach(struct device *parent, struct device *sel
PHY_WRITE(sc, E1000_GCR1, reg);
PHY_WRITE(sc, E1000_EADR, page);
}
+
+ if (sc->mii_model == MII_MODEL_MARVELL_E1512 &&
+ (sc->mii_flags & MIIF_SETDELAY)) {
+ page = PHY_READ(sc, E1000_EADR);
+ PHY_WRITE(sc, E1000_EADR, 2);
+ reg = PHY_READ(sc, E1000_MSCR2);
+ reg &= ~E1000_MSCR2_DELAY_MASK;
+ if (sc->mii_flags & MIIF_RXID)
+ reg |= E1000_MSCR2_RXDELAY;
+ if (sc->mii_flags & MIIF_TXID)
+ reg |= E1000_MSCR2_TXDELAY;
+ PHY_WRITE(sc, E1000_MSCR2, reg);
+ PHY_WRITE(sc, E1000_EADR, page);
+ }
PHY_RESET(sc);
blob - 59c6c5678987cecde898f44c77b6046a9b7b672f
file + sys/dev/mii/eephyreg.h
--- sys/dev/mii/eephyreg.h
+++ sys/dev/mii/eephyreg.h
@@ -331,3 +331,10 @@
#define E1000_GCR1_RESET 0x8000
#define E1000_GCR1_MODE_MASK 0x0007
#define E1000_GCR1_MODE_SGMII 0x0001
+
+/* The following register is found only on the 88E151x Alaska PHY */
+/* Page 2 */
+#define E1000_MSCR2 0x15 /* MAC-Specific Control Register 2 */
+#define E1000_MSCR2_RXDELAY 0x20
+#define E1000_MSCR2_TXDELAY 0x10
+#define E1000_MSCR2_DELAY_MASK 0x30
