Hi I think that adding ADC zero and gain drift would be a good idea.
Considering that the hardware will be doing an early/on-time/late calibration cycle every second in between PPS pulses, it should be relatively safe to assume that drift will be calibrated out, no? If you keep the ADC/uC in still air the draft time constant should be long compared to the calibration tc.
(It is a great pity that ADC INL is hard to model). JD 'draft causes drift' B. -- LART. 250 MIPS under one Watt. Free hardware design files. http://www.lartmaker.nl/ _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
