At 08:30 +1200 14-08-2010, Bruce Griffiths wrote:
J.D. Bakker wrote:
4) If the ADC(s) have a sufficiently wide full power bandwidth
then one could just sample a pair of quadrature phased 250kHz
sinewaves.
As someone who's used to thinking in I/Q I must say I've always
liked the elegance of this approach. Trouble is that I don't see a
cheap/easy way to generate quadrature sines with low enough
distortion/noise.
Distortion isnt a great problem if its relatively small and stable
as it can always be measured as part of the calibration process and
its effect may then be compensated in software.
Those are two large "if"s, if you're going for a small/cheap
implementation. Fully analog solutions can get messy, phase shifter
hybrids are doable but would definitely need to be shielded from
drafts and DDSes plus appropriate filters do the job but are still
relatively expensive. And then there's motor/generators... Am I
missing any method here?
(on a semi-related note: some interesting work on ultralow distortion
low frequency oscillators, employing quadrature signals to simplify
the AGC, is being done here:
<http://www.prodigy-pro.com/diy/index.php?topic=26461.0>)
(I'm not sure why I'd want to use a synchronizer in this path. The
way I see it the TAC operates as a linear phase detector, with the
GPS PPS and the synthesized PPS as inputs. The microcontroller then
applies the sawtooth correction to the measured time offset, and
uses the result in a DPLL. There will, of course, be a synchronizer
in the input line from the GPS PPS to the microcontroller, but
that's only used for the FLL and for rough synchronization).
Using a synchroniser allows the TAC output range to be combined with
the coarse timestamp derived by sampling a counter clocked by the
same clock as the synchroniser.
I think we're looking at it from two different angles.
What I read from your description is close to the traditional
architecture such as used in the HP5335A, with a counter running at
the system clock frequency for coarse measurement and a TAC to
measure the remainder. What I'm planning to do is more akin a
traditional PLL, with the TAC as the Phase Detector. For this to work
I assume that a coarse FLL (using a counter) has already brought the
oscillator within lock range. Is there any reason that method won't
work, or can trivially be made to work better?
(The regenerated PPS output will indeed be derived from and
synchronous with the VCXO/OCXO. It is also my intention to have the
OCXO clock the microcontroller, either directly or through a
prescaler, depending on whether the XO runs higher or lower than the
max CPU clock).
- Circuit 3 expands on this approach by having dual ramp
generators, and having the ADC measure the voltage difference
between the two.
Not a good idea, as this requires accurate matching of the gains
of the 2 TACs.
Why?
At that points they're not TACs yet, just ramp generators. Circuit
3 uses the difference between these ramps, and I believe it need
not be constant.
Assume there's a 1% difference in ramp rates; say C3 charges at
1V/us and C4 charges at 1.01V/us. [...]
Since NP0/C0G caps are only available in 5% and 10% tolerance at
best, matching gains to 1% will require using selected parts (adjust
current source to compensate) or trimming.
I picked the 1% figure out of the air, simply to have an example for
the math. Even so, if required it would be easy to have the
microcontroller trim the ramp rates through one of the on-chip DACs.
However I don't believe that the ramp rate can't be dealt with in
software through calibration.
Simulation indicates nonlinearity of the order of 1% or so in the
ramp generator. This is largely due to the Early effect and
semiconductor output capacitance modulation.
Yeah, I noticed that. It helps a lot in the four-transistor mirror to
have all transistors carry approximately equal amounts of current.
Further linearization can be achieved by increasing the current,
slowing the ramp rate and picking transistors with lower hFE for a
given fT and/or higher VAF. An output resistance of up to 1M can be
achieved, but it's the voltage-dependent capacitance that's hurting
linearity.
(I'm still not set on a given ramp rate, but the more I think about
it the more I feel that it makes sense to go lower than the 1V/us I
picked earlier. Many of the nonlinearities in the current source,
buffer amps and ADC get worse with increasing slew rate, and as long
as the total ramp time is << the interval between measurements there
should be no major issues there either. Sample clock drift could be
an issue, but as the ADC is driven by the OCXO that shouldn't impact
matters either).
The output compliance of your four transistor current mirror is
limited to around 1.3V or so before the onset of saturation or gross
nonlinearity.
It's actually better than that, from what I can see from simulations
and measurements. If the transistor currents are close to equal and
the ramp rate isn't too high, output current stays within 1% up to
~1V, and the mirror saturates at 0.6-0.7V. This is with common
small-signal transistors with an fT of a few hundred MHz.
Unless the transistors are closely thermally coupled some resistance
in the emitters of the CE transistors may be required to avoid
thermal runaway.
While I plan to use some of those newer dual transistors in SOT-23-6
to improve thermal coupling, I'll probably add a few VsubT worth of
emitter resistance there.
Thanks again,
JDB.
[I should probably make a sketch of the entire GPSDO and post it]
--
LART. 250 MIPS under one Watt. Free hardware design files.
http://www.lartmaker.nl/
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