Yet another option is to sample the output of a simple 1us time constant
RC low pass filter and fit an exponential to the sampled data and
calculate the threshold crossing from this.
If the aberrations are sufficiently low over the range of time intervals
measured (0.5us to 1us with a conventional 2 stage synchroniser clocked
at 2MHz) this would be the simplest solution in that it only requires a
single resistor and a single capacitor.
Bruce
Bruce Griffiths wrote:
Yes, with a 2MSPS ADC and 1-2us transition times one gets 2-4 samples
during the transition.
Worst case with a 1us filter (10%-90%) output transition time there
may be one sample at the midpoint and samples close to the 10% and 90%
amplitude points.
2us transition times are probably close to optimum.
In the latter case the effective time stamp resolution (with a true 12
bit ADC) will be around 0.5ns.
Ideally a gaussian impulse response filter should be used.
However if the input transitions are sufficiently (to allow the filter
transients to settle) far apart almost any reasonable (without
excessive overshoot) could be used.
The minicircuits LPF_BOR3+ low pass filter appears almost good enough.
Bruce
Bob Camp wrote:
Hi
Would't you want 2 or more samples during the transition?
Bob
On Aug 12, 2010, at 8:25 PM, Bruce
Griffiths<bruce.griffi...@xtra.co.nz> wrote:
Another method is to attenuate (to within the ADC input range) the
PPS signal to be timestamped, low pass filter it and capture a 2MSPS
sample burst centred around the low pass filter output transition
midpoint.
You can then use WKS interpolation to time stamp the transition
midpoint (when it crosses a threshold halfway between the initial
and final values of the low pass filter output).
The low pass filter (preferably an LC filter) delay is easily
calibrated by timestamping an internally generated signal initiated
on a known ADC sampling clock edge.
No (external) current sources, reset switches etc are required.
With a 2MSPS sample rate a low pass filter output transition time of
1-2us should suffice (provided the ADC has a sufficiently large
large signal bandwidth).
Bruce
Bruce Griffiths wrote:
Some options:
1) Use a 74AHC05 for Q1 and Q2.
2) Switch the current source at the emitter node and only turn on
the current source when charging the capacitor.
This will increase the available TAC output voltage range and/or
improve the linearity by eliminating the diode.
However the capacitor discharge switch should be turned off before
charging the capacitor.
A stable fixed delay of a few (10ns??) before switching on the
current source is required.
3) Replace the current source with a resistor.
The resultant nonlinearity is well defined and software correction
should be relatively easy.
4) If the ADC(s) have a sufficiently wide full power bandwidth then
one could just sample a pair of quadrature phased 250kHz sinewaves.
Extend the range by sampling (synchronise the input sampling edge
to the counter clock first) a counter clocked at 250KHz.
Initiate the sampling with the signal edge to be time stamped.
If the GPSDO is used to clock the microprocessor, counters and
produce the quadrature sinewave outputs then only a single TDC
(time to digital converter) is required.
Measuring negative time intervals should not be necessary as the
TAC (or other TDC) should be used merely to measure the delay of a
synchroniser the output of which is used to synchronously sample a
counter clocked with the same clock as the synchroniser.
J.D. Bakker wrote:
Hello all,
I'm working on Yet Another DIY GPSDO, and one of the issues I've
been looking into is a TAC/TDC to do sawtooth correction on the
measurement of the GPS PPS signal. I'd like to stick with a 3.3V
supply for most of the circuit, and several of the TAC designs
that have been discussed here in the past run into trouble at such
low voltages (mostly through VBE drops).
To start with the context: I'm planning to use a microcontroller
with a built-in dual 12-bit 2MSPS ADC. I'd like to not use
anything that's not available at Digi-Key or Mouser, and keep the
SMD pitch>=0.8mm (with a possible exception for dual transistors
in SOT-23-6). That way the design shouldn't be too hard for others
to replicate.
I'm aiming for a TAC accuracy of 1ns, allowing for one or a few
calibrations between PPS pulses. Minimum full-scale range should
be +/- a few hundred ns, to allow for outliers. (The plan is to
have an initial FLL for coarse locking, and have the PLL kick in
after that). I'm penciling in an ADC reference voltage of 2V, as
that's commonly available and leaves enough headroom to use the
current sources in their most linear range.
I've attached a diagram that reflects a few of my current thoughts.
- Circuit 1 is the traditional TAC. Before the start of the cycle
Q2 conducts, discharging C1 and shunting I1's current to ground.
At this point the ADC can measure the voltage drop across C1/Q2 to
eliminate that offset. Taking nSTART low puts Q2 into
high-impedance, and I1 charges C1 through D1 until STOP is raised
causing Q1 to shunt I1's current to ground. At this point the ADC
samples the voltage across C1, which is proportional to the time
between START and STOP (modulo offset and nonlinearities).
This circuit is well known to work (although it is more common to
use Q1 for both START and STOP and to limit Q2 to ramp discharge
duties). Downsides are that negative time offsets cannot be
measured directly, and the constant output voltage offers little
room for increased precision through sample averaging, unless the
ADC's input noise is large compared to its LSB size. For the same
reason there is no easy way to reduce the effects of ADC INL/DNL.
- Circuit 2 works in a similar way, except that the ramp isn't
terminated by a STOP signal but is allowed to run freely until I2
saturates. The ADC is set to sample continuously, taking multiple
samples of the ramp, and the microcontroller interpolates the
resulting values to determine the elapsed time between an internal
time reference point and the START signal.
This circuit is fairly simple, and has the advantage that there is
no hard limit to its range. Curve-fitting the sampled values
increases precision and reduces the effects of INL/DNL. On the
other hand, ADC aperture jitter and offset have a direct impact on
resolution.
- Circuit 3 expands on this approach by having dual ramp
generators, and having the ADC measure the voltage difference
between the two.
Not a good idea, as this requires accurate matching of the gains of
the 2 TACs.
Its better to sample each TAC output individually as this allows
software correction for gain mismatch (and nonlinearity) before
subtraction.
Software correction is better than using trimpots or similar as the
parasitics etc associated with trimpots are eliminated.
This approach is the only one of the three that can directly
measure negative time offsets, allowing a regenerated pulse to be
directly compared with the GPS' PPS. A small difference in ramp
rates, unavoidable in practice, actually helps to average out DNL
and is easily corrected in calibration. Sampling time uncertanties
have less impact than in Circuit 2. Then again, it may be
difficult to reliably detect the start/end-of-ramp points from the
samples alone. Total range is relatively limited, and due to the
differential measurements it is harder to reduce current source
nonlinearities in software.
Any thoughts? At this point I'm tempted to build a hybrid of 2 and
3, using one of the microcontroller's ADCs in each mode.
I've not seen prior work on the ramp-approach, although it's a
close cousin to the centroid pulse timing method
(<http://www.febo.com/pipermail/time-nuts/2006-September/021765.html>).
Has anyone seen it before (and possibly shot down due to major
deficiencies)? It seems too obvious to not have been considered by
others.
It was usually not feasible as the ADC's typically used had
insufficient input power bandwidth.
The settling time and power bandwidth of any buffer amplifier
between the ramp capacitor and the ADC has also to be considered.
If one uses a capacitive input charge redistribution ADC connected
directly to the ramp capacitor then the sampling process itself
transfers charge from the ramp capacitor to the sampling capacitor.
Software compensation for this effect may be required as the
transferred charge depends on the number of samples from the ramp
start to the current sample.
You will also need to ensure that the current source recovers
sufficiently quickly from saturation.
Another issue is to limit the discharge current flowing in the
discharge switch.
Often a 2 step discharge is used.
A switch with a series resistor is used to discharge the capacitor
to the point at which the second switch can be turned on to
complete the discharge without excessive curent flowing in this
switch. See the HP53131A/2A schematics for an example.
(Notes: These are initial rough sketches. The ramp current has not
been optimized yet; I have an unsubstantiated feeling that
brute-forcing it with a higher current and larger cap may well
help to swamp some of the nonlinearities. I've mostly picked 1V/us
ramp speed out of the air because it gives me 4-5 samples @2MSPS
which is a workable number to do curve fitting on. Also not sure
whether I'll use the simpler one-transistor current source or the
hi-Zout mirror with a current source derived from the ADC's
reference. The FETs may end up being implemented as single-gate
/OE drivers. I'll do a more complete write-up on the entire GPSDO
later).
Thanks,
JDB.
Bruce
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