Thank you for your comments. Replies inline:
At 11:37 +1200 13-08-2010, Bruce Griffiths wrote:
1) Use a 74AHC05 for Q1 and Q2.
I was looking at the 74LVC1G07. It's a single gate, so probably less
package parasitics to worry about. Output capacitance is actually
specified (5pF typ); charge injection might be a bit higher than the
AHC part. As its output is 5V tolerant, it might be worthwhile
running it at a lower voltage to reduce injection (but maybe that's
premature optimization at this stage).
3) Replace the current source with a resistor.
The resultant nonlinearity is well defined and software correction
should be relatively easy.
(and, from a later message):
At 17:59 +1200 13-08-2010, Bruce Griffiths wrote:
Yet another option is to sample the output of a simple 1us time
constant RC low pass filter and fit an exponential to the sampled
data and calculate the threshold crossing from this.
I've considered this, and haven't entirely rejected it yet. The
hardware simplicity is appealing. On the other hand, a linear ramp
gives equal exposure to the entire code range of the (linear) ADC,
which is better for averaging out noise and ADC nonlinearities. Even
with the dual ramp configuration and the more complex current mirror
the increase in BOM cost is less than a dollar, all in parts that
have multiple sources and are easy to get.
4) If the ADC(s) have a sufficiently wide full power bandwidth then
one could just sample a pair of quadrature phased 250kHz sinewaves.
As someone who's used to thinking in I/Q I must say I've always liked
the elegance of this approach. Trouble is that I don't see a
cheap/easy way to generate quadrature sines with low enough
distortion/noise.
Measuring negative time intervals should not be necessary as the TAC
(or other TDC) should be used merely to measure the delay of a
synchroniser the output of which is used to synchronously sample a
counter clocked with the same clock as the synchroniser.
I want to have a GPS-synchronized PPS output. I believe that the
uncorrected PPS from some GPS modules (including the M12?) can be
both early and late, so I need some way to account for this. While I
can of course generate an early PPS for the TAC to provide an offset
of a few hundred ns, I'd prefer to tap the actual (synthesized) PPS
output so that the output driver's delay drift is inside the loop.
Naturally I have to take care that loading on this output doesn't end
up pulling the GPSDO in that scenario.
(I'm not sure why I'd want to use a synchronizer in this path. The
way I see it the TAC operates as a linear phase detector, with the
GPS PPS and the synthesized PPS as inputs. The microcontroller then
applies the sawtooth correction to the measured time offset, and uses
the result in a DPLL. There will, of course, be a synchronizer in the
input line from the GPS PPS to the microcontroller, but that's only
used for the FLL and for rough synchronization).
- Circuit 3 expands on this approach by having dual ramp
generators, and having the ADC measure the voltage difference
between the two.
Not a good idea, as this requires accurate matching of the gains of
the 2 TACs.
Why?
At that points they're not TACs yet, just ramp generators. Circuit 3
uses the difference between these ramps, and I believe it need not be
constant.
Assume there's a 1% difference in ramp rates; say C3 charges at 1V/us
and C4 charges at 1.01V/us. When the ramps are started
simultaneously, the difference between ramp voltages (ignoring
saturation) is simply 0.01t (in us). When one ramp is started 1ns
earlier than the other, the difference (during the time that both
ramps are active) is 0.001 + 0.01t. I believe that this linear factor
is easy to calibrate out with regular early/on-time/late calibration.
I am somewhat concerned that in this scenario it may be harder for
software to detect the point that both ramps are running from sampled
values alone, and nonlinearities in the current source are harder to
calibrate out. Still I believe the basic scheme should work fine. Am
I missing something?
You will also need to ensure that the current source recovers
sufficiently quickly from saturation.
In the most intensive calibration regime I'm looking at now
(early/on-time/late every second) I'd have four measurements per
second, so the current source has the better part of 250ms to
recover. That won't be a problem for the four-transistor mirror; I'd
have to do the math with actual part values to be sure with the
simple version.
Another issue is to limit the discharge current flowing in the
discharge switch.
I know, I left that out for clarity. A small drop across the
discharge switch/limiting resistor needn't be a problem, given that
many single-supply converters and buffers are happier if their input
is ~100mV above ground.
Thanks again,
JDB.
--
Years from now, if you are doing something quick and dirty,
you imagine that I am looking over your shoulder and say to
yourself, "Dijkstra would not like this," well that would be
immortality for me. -- Edsger Dijkstra, 1930 - 2002
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