On Sat, 6 Jun 2015 09:52:11 -0400 Bob Camp <kb...@n1k.org> wrote: > > Was it a simple > > counter or was there enable/up/down/load type gating involved? > > > > What would you have done if you needed to run a bit faster? > > Bought a faster FPGA or gone to an ASIC. > > > Could you buy a > > faster chip? > > For enough money there’s always a faster chip :)
Even if it is OT, to give this a little economic perspective: Today, an ASIC starts to be cheaper than an FPGA solution at production volumes somewhere between 1000 and 10'000 pieces (in total). If you have working (synchronous) VHDL code, going ASIC is pretty straight forward and is mostly automatic. There are several fabs in Europe and Asia that offer node sizes between 180nm and 35nm for even very small runs and help you to convert your FPGA code to proper ASIC designs. A simple ASIC project is cheap enough, that some universities offer courses where students (in a master course) design their own chips, let them produce and measure their performance later, all cost covered by the university. (If i remember correctly, the cost was around 10kUSD per design and for 20 dies, half of them in QFP, half as nacked die) Attila Kinali -- It is upon moral qualities that a society is ultimately founded. All the prosperity and technological sophistication in the world is of no use without that foundation. -- Miss Matheson, The Diamond Age, Neil Stephenson _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.