Hi Last time I saw university multi project wafer prices, the cost was around $5K for a run on a “not state of the art” fab process. That included absolutely nothing in the way of design assistance. It was strictly “we fab what you told us to do”. The “run date” for the chips was also a bit vague. They used space on other design runs, so you got about a 3 month window on when your parts might run. Eventually you got back a waffle pack with some die to go wire bond up.
Often the trick was to take the work of several students and put in on a single chip. The *hope* was that nothing pathogenic happened in any of the designs to render the whole thing useless. The gotcha on ASIC’s os (of course) the running cost of this stuff. If you are using a bunch of parts is’t not to bad. If not, the phone call every 4 years or so about “you need to buy a new mask set for $XXX,XXX” gets a bit old. For a state of the art process add at least one more X to that number. Coming back to timing. Once you go to an ASIC, the ability to optimize for low jitter / good ADEV (or whatever) comes into the picture. There is no reason why there should be any worse performance on the ASIC than on any logic family you can find. All of the previous caveats about phase noise floors go away. That’s not to say that things like crosstalk between two pads that are 0.05 mm apart suddenly vanishes. You still have to take care of the i/o part of the design. Bob > On Jun 6, 2015, at 1:49 PM, Attila Kinali <att...@kinali.ch> wrote: > > On Sat, 6 Jun 2015 09:52:11 -0400 > Bob Camp <kb...@n1k.org> wrote: > >>> Was it a simple >>> counter or was there enable/up/down/load type gating involved? >>> >>> What would you have done if you needed to run a bit faster? >> >> Bought a faster FPGA or gone to an ASIC. >> >>> Could you buy a >>> faster chip? >> >> For enough money there’s always a faster chip :) > > Even if it is OT, to give this a little economic perspective: > Today, an ASIC starts to be cheaper than an FPGA solution at production > volumes somewhere between 1000 and 10'000 pieces (in total). > If you have working (synchronous) VHDL code, going ASIC is pretty > straight forward and is mostly automatic. There are several fabs > in Europe and Asia that offer node sizes between 180nm and 35nm > for even very small runs and help you to convert your FPGA code > to proper ASIC designs. > > A simple ASIC project is cheap enough, that some universities offer > courses where students (in a master course) design their own chips, > let them produce and measure their performance later, all cost covered > by the university. (If i remember correctly, the cost was around 10kUSD > per design and for 20 dies, half of them in QFP, half as nacked die) > > Attila Kinali > > > -- > It is upon moral qualities that a society is ultimately founded. All > the prosperity and technological sophistication in the world is of no > use without that foundation. > -- Miss Matheson, The Diamond Age, Neil Stephenson > _______________________________________________ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
