Am 29.06.20 um 18:43 schrieb jimlux:
What logic family might be appropriate for a divide by 5 from 50 to
10MHz, low power, running off 3.3 or 5V?
In the picture is probably what you need, and maybe more.
The left third is a comparator that generates valid CMOS levels from a
vaguely defined sine signal.
The right third determines if there is a valid reference and tells the
PLL (not in the picture) to use
or ignore it.
If you have a valid CMOS signal, the middle is all that is needed.
LVC163 + LVC04. Good enough for
150 MHz+. On terminal count, the inverter forces the counter to load
the P0..3 pins on the next
clock. The value on P0..3 determines the division ratio, from 2 to 16.
Large numbers = few clocks
until the next terminal count. The example is divide by 5, which happens
to fit your problem.
IIRC, the 74AC191 could have done that without the external inverter,
but it did not make it
into the 74LVC series.
That's what I used to lock my DG8SAQ vector network analyzer V2+ to an
external 10 MHz reference
before that was available in V3. The PLL chip was a 74lvc4046.
https://www.digikey.de/product-detail/de/nexperia-usa-inc/74LVC163PW-118/1727-3097-2-ND/946683
Cheers, Gerhard
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