Am 01.07.20 um 03:04 schrieb Hal Murray:
What logic family might be appropriate for a divide by 5 from 50 to 10MHz,
low power, running off 3.3 or 5V?
How important is the "low" power? Do you have other logic/CPU around?
Do you need 50/50 duty cycle (or close) or is 20/80 OK?
How about a CPU with a counter/timer block setup to divide by 5 and the CPU
sleeping (if it doesn't have anything else to do)?
What is available in the small FPGA or PAL space?
In the divide-by-81 thread I have proposed a Xilinx Coolrunner, with
VHDL code, and a link to a prefabricated Chinese board. Just replace
the 81 by 5 and choose the new On/Off ratio.
<
https://www.digikey.de/product-detail/de/xilinx-inc/XC2C64A-5VQG44C/122-1420-ND/966601
>
Prices are slowly rising, that's Xilinx' way of saying: we don't like it
anymore,
but we usually don't obsolete anything.
I'm just doing a custom reciprocal frequency counter with SPI interface
in one,
and my crystal oven infrastructure board uses such a 2C64 for its 1pps
generator
and switchable direction 2FF phase detector. You can do a lot of things
with just 64
flipflops. It's weird, but Coolrunner Flipflops can act on both rising
and falling
clock edge if required.
Much modern logic is aimed at the high speed market which usually means thin
oxide which leaks. I'm pretty sure I've seen some FPGA/PAL families that are
old but still very active just because their idle power is very low - the last
family before things started to leak.
When it was new, Xilinx demonstrated the Coolrunner with a battery
made from 3 apples or oranges and some wire.
How about a shift register? It needs a reset signal to get started.
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