> What logic family might be appropriate for a divide by 5 from 50 to 10MHz, > low power, running off 3.3 or 5V?
How important is the "low" power? Do you have other logic/CPU around? Do you need 50/50 duty cycle (or close) or is 20/80 OK? How about a CPU with a counter/timer block setup to divide by 5 and the CPU sleeping (if it doesn't have anything else to do)? What is available in the small FPGA or PAL space? Much modern logic is aimed at the high speed market which usually means thin oxide which leaks. I'm pretty sure I've seen some FPGA/PAL families that are old but still very active just because their idle power is very low - the last family before things started to leak. How about a shift register? It needs a reset signal to get started. -- These are my opinions. I hate spam. _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.
