Hi Kumar, Kumar Gala wrote: > The MPC8544 RM incorrect shows the SEC_CFG bit in PORDEVSR2 as being > bit 26, instead it should be bit 28. This caused in incorrect > interpretation of the i2c_clk which is the same as the SEC clk on > MPC8544. The SEC clk is controlled by cfg_sec_freq that is reported > in PORDEVSR2. > > Signed-off-by: Kumar Gala <[EMAIL PROTECTED]>
That makes sense now. I just got the confirmation from the customer, that LWE_B[0] is indeed pulled down via FPGA: LWE_B[0] Pulldown SEC Frequency Ratio 2:1 Thanks for your investigations. Wolfgang. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot