The PAD declarations for PL301 pad settings were pretty haphazard
and this patch consolidates the pad names to make it easy to
compare the functions between i.MX6Q and i.MX6DLS.
The new forms of these declarations do not match Freescale's
Linux 3.x headers, where those inconsistencies are also present.
No functional changes are introduced by this patch and
there are no current users of these declarations.
Signed-off-by: Eric Nelson <eric.nel...@boundarydevices.com>
---
arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 90 +++++++++++++++---------------
arch/arm/include/asm/arch-mx6/mx6q_pins.h | 66 +++++++++++-----------
2 files changed, 78 insertions(+), 78 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
index c3d0b70..21ca67a 100644
--- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h
@@ -190,7 +190,7 @@ enum {
MX6_PAD_DI0_PIN15__SDMA_DEBUG_CORE_STATE_1 = IOMUX_PAD(0x03B4,
0x00A0, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN15__GPIO_4_17 = IOMUX_PAD(0x03B4, 0x00A0, 5,
0x0000, 0, 0),
MX6_PAD_DI0_PIN15__MMDC_MMDC_DEBUG_1 = IOMUX_PAD(0x03B4, 0x00A0, 6,
0x0000, 0, 0),
- MX6_PAD_DI0_PIN15__PL301_SIM_MX6DL_PER1_HSIZE_0 = IOMUX_PAD(0x03B4,
0x00A0, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN15__PL301_PER1_HSIZE_0 = IOMUX_PAD(0x03B4, 0x00A0, 7,
0x0000, 0, 0),
MX6_PAD_DI0_PIN15__LCDIF_RD_E = IOMUX_PAD(0x03B4, 0x00A0, 8,
0x0000, 0, 0),
MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2 = IOMUX_PAD(0x03B8, 0x00A4, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN2__LCDIF_HSYNC = IOMUX_PAD(0x03B8, 0x00A4, 1,
0x08D8, 0, 0),
@@ -199,7 +199,7 @@ enum {
MX6_PAD_DI0_PIN2__SDMA_DEBUG_CORE_STATE_2 = IOMUX_PAD(0x03B8,
0x00A4, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN2__GPIO_4_18 = IOMUX_PAD(0x03B8, 0x00A4, 5,
0x0000, 0, 0),
MX6_PAD_DI0_PIN2__MMDC_MMDC_DEBUG_2 = IOMUX_PAD(0x03B8, 0x00A4, 6,
0x0000, 0, 0),
- MX6_PAD_DI0_PIN2__PL301_SIM_MX6DL_PER1_HADDR_9 = IOMUX_PAD(0x03B8,
0x00A4, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN2__PL301_PER1_HADDR_9 = IOMUX_PAD(0x03B8, 0x00A4, 7,
0x0000, 0, 0),
MX6_PAD_DI0_PIN2__LCDIF_RS = IOMUX_PAD(0x03B8, 0x00A4, 8,
0x0000, 0, 0),
MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3 = IOMUX_PAD(0x03BC, 0x00A8, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN3__LCDIF_VSYNC = IOMUX_PAD(0x03BC, 0x00A8, 1,
0x0000, 0, 0),
@@ -208,7 +208,7 @@ enum {
MX6_PAD_DI0_PIN3__SDMA_DEBUG_CORE_STATE_3 = IOMUX_PAD(0x03BC,
0x00A8, 4, 0x0000, 0, 0),
MX6_PAD_DI0_PIN3__GPIO_4_19 = IOMUX_PAD(0x03BC, 0x00A8, 5,
0x0000, 0, 0),
MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x03BC, 0x00A8, 6,
0x0000, 0, 0),
- MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 = IOMUX_PAD(0x03BC,
0x00A8, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN3__PL301_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7,
0x0000, 0, 0),
MX6_PAD_DI0_PIN3__LCDIF_CS = IOMUX_PAD(0x03BC, 0x00A8, 8,
0x0000, 0, 0),
MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DI0_PIN4__LCDIF_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1,
0x08D8, 1, 0),
@@ -217,7 +217,7 @@ enum {
MX6_PAD_DI0_PIN4__SDMA_DEBUG_YIELD = IOMUX_PAD(0x03C0, 0x00AC, 4,
0x0000, 0, 0),
MX6_PAD_DI0_PIN4__GPIO_4_20 = IOMUX_PAD(0x03C0, 0x00AC, 5,
0x0000, 0, 0),
MX6_PAD_DI0_PIN4__MMDC_MMDC_DEBUG_4 = IOMUX_PAD(0x03C0, 0x00AC, 6,
0x0000, 0, 0),
- MX6_PAD_DI0_PIN4__PL301_SIM_MX6DL_PER1_HADDR_11 = IOMUX_PAD(0x03C0,
0x00AC, 7, 0x0000, 0, 0),
+ MX6_PAD_DI0_PIN4__PL301_PER1_HADDR_11 = IOMUX_PAD(0x03C0, 0x00AC, 7,
0x0000, 0, 0),
MX6_PAD_DI0_PIN4__LCDIF_RESET = IOMUX_PAD(0x03C0, 0x00AC, 8,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT0__LCDIF_DAT_0 = IOMUX_PAD(0x03C4, 0x00B0, 1,
0x0000, 0, 0),
@@ -226,7 +226,7 @@ enum {
MX6_PAD_DISP0_DAT0__SDMA_DEBUG_CORE_RUN = IOMUX_PAD(0x03C4, 0x00B0, 4,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__GPIO_4_21 = IOMUX_PAD(0x03C4, 0x00B0, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT0__MMDC_MMDC_DEBUG_5 = IOMUX_PAD(0x03C4, 0x00B0, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT0__PL301_SIM_MX6DL_PER1_HSIZE_1 =
IOMUX_PAD(0x03C4, 0x00B0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT0__PL301_PER1_HSIZE_1 = IOMUX_PAD(0x03C4, 0x00B0, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT1__LCDIF_DAT_1 = IOMUX_PAD(0x03C8, 0x00B4, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__ECSPI3_MOSI = IOMUX_PAD(0x03C8, 0x00B4, 2,
0x0000, 0, 0),
@@ -234,41 +234,41 @@ enum {
MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL =
IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x03C8, 0x00B4, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__MMDC_MMDC_DEBUG_6 = IOMUX_PAD(0x03C8, 0x00B4, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT1__PL301_SIM_MX6DL_PER1_HADDR_12 =
IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__PL301_PER1_HADDR_12 = IOMUX_PAD(0x03C8, 0x00B4, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 0,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__LCDIF_DAT_10 = IOMUX_PAD(0x03CC, 0x00B8, 1,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT10__USDHC1_USDHC_DEBUG_6 = IOMUX_PAD(0x03CC,
0x00B8, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x03CC,
0x00B8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x03CC, 0x00B8, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__MMDC_MMDC_DEBUG_15 = IOMUX_PAD(0x03CC, 0x00B8, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT10__PL301_SIM_MX6DL_PER1_HADDR_21 =
IOMUX_PAD(0x03CC, 0x00B8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__PL301_PER1_HADDR_21 = IOMUX_PAD(0x03CC,
0x00B8, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT11__LCDIF_DAT_11 = IOMUX_PAD(0x03D0, 0x00BC, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DEBUG_7 = IOMUX_PAD(0x03D0,
0x00BC, 3, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x03D0,
0x00BC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x03D0, 0x00BC, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__MMDC_MMDC_DEBUG_16 = IOMUX_PAD(0x03D0, 0x00BC, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT11__PL301_SIM_MX6DL_PER1_HADDR_22 =
IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__PL301_PER1_HADDR_22 = IOMUX_PAD(0x03D0,
0x00BC, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT12__LCDIF_DAT_12 = IOMUX_PAD(0x03D4, 0x00C0, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x03D4,
0x00C0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x03D4, 0x00C0, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__MMDC_MMDC_DEBUG_17 = IOMUX_PAD(0x03D4, 0x00C0, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT12__PL301_SIM_MX6DL_PER1_HADDR_23 =
IOMUX_PAD(0x03D4, 0x00C0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__PL301_PER1_HADDR_23 = IOMUX_PAD(0x03D4,
0x00C0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT13__LCDIF_DAT_13 = IOMUX_PAD(0x03D8, 0x00C4, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x03D8, 0x00C4, 3,
0x07BC, 0, 0),
MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x03D8,
0x00C4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x03D8, 0x00C4, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__MMDC_MMDC_DEBUG_18 = IOMUX_PAD(0x03D8, 0x00C4, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT13__PL301_SIM_MX6DL_PER1_HADDR_24 =
IOMUX_PAD(0x03D8, 0x00C4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__PL301_PER1_HADDR_24 = IOMUX_PAD(0x03D8,
0x00C4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT14__LCDIF_DAT_14 = IOMUX_PAD(0x03DC, 0x00C8, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03DC, 0x00C8, 3,
0x07B8, 0, 0),
MX6_PAD_DISP0_DAT14__SDMA_DEBUG_EVT_CHN_LINES_1 = IOMUX_PAD(0x03DC,
0x00C8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__GPIO_5_8 = IOMUX_PAD(0x03DC, 0x00C8, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__MMDC_MMDC_DEBUG_19 = IOMUX_PAD(0x03DC, 0x00C8, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT14__PL301_SIM_MX6DL_PER1_HSIZE_2 =
IOMUX_PAD(0x03DC, 0x00C8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT14__PL301_PER1_HSIZE_2 = IOMUX_PAD(0x03DC, 0x00C8, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT15__LCDIF_DAT_15 = IOMUX_PAD(0x03E0, 0x00CC, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__ECSPI1_SS1 = IOMUX_PAD(0x03E0, 0x00CC, 2,
0x07E8, 0, 0),
@@ -276,7 +276,7 @@ enum {
MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x03E0,
0x00CC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x03E0, 0x00CC, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__MMDC_MMDC_DEBUG_20 = IOMUX_PAD(0x03E0, 0x00CC, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT15__PL301_SIM_MX6DL_PER1_HADDR_25 =
IOMUX_PAD(0x03E0, 0x00CC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__PL301_PER1_HADDR_25 = IOMUX_PAD(0x03E0,
0x00CC, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT16__LCDIF_DAT_16 = IOMUX_PAD(0x03E4, 0x00D0, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x03E4, 0x00D0, 2,
0x07FC, 1, 0),
@@ -284,7 +284,7 @@ enum {
MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x03E4,
0x00D0, 4, 0x08E8, 0, 0),
MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x03E4, 0x00D0, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__MMDC_MMDC_DEBUG_21 = IOMUX_PAD(0x03E4, 0x00D0, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT16__PL301_SIM_MX6DL_PER1_HADDR_26 =
IOMUX_PAD(0x03E4, 0x00D0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__PL301_PER1_HADDR_26 = IOMUX_PAD(0x03E4,
0x00D0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT17__LCDIF_DAT_17 = IOMUX_PAD(0x03E8, 0x00D4, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x03E8, 0x00D4, 2,
0x07F8, 1, 0),
@@ -292,7 +292,7 @@ enum {
MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x03E8,
0x00D4, 4, 0x08EC, 0, 0),
MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x03E8, 0x00D4, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__MMDC_MMDC_DEBUG_22 = IOMUX_PAD(0x03E8, 0x00D4, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT17__PL301_SIM_MX6DL_PER1_HADDR_27 =
IOMUX_PAD(0x03E8, 0x00D4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__PL301_PER1_HADDR_27 = IOMUX_PAD(0x03E8,
0x00D4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT18__LCDIF_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x03EC, 0x00D8, 2,
0x0800, 1, 0),
@@ -316,7 +316,7 @@ enum {
MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x03F4, 0x00E0, 4,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x03F4, 0x00E0, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__MMDC_MMDC_DEBUG_7 = IOMUX_PAD(0x03F4, 0x00E0, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT2__PL301_SIM_MX6DL_PER1_HADDR_13 =
IOMUX_PAD(0x03F4, 0x00E0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__PL301_PER1_HADDR_13 = IOMUX_PAD(0x03F4, 0x00E0, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT20__LCDIF_DAT_20 = IOMUX_PAD(0x03F8, 0x00E4, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__ECSPI1_SCLK = IOMUX_PAD(0x03F8, 0x00E4, 2,
0x07D8, 1, 0),
@@ -324,7 +324,7 @@ enum {
MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x03F8,
0x00E4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x03F8, 0x00E4, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__MMDC_MMDC_DEBUG_25 = IOMUX_PAD(0x03F8, 0x00E4, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT20__PL301_SIM_MX6DL_PER1_HADDR_28 =
IOMUX_PAD(0x03F8, 0x00E4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__PL301_PER1_HADDR_28 = IOMUX_PAD(0x03F8,
0x00E4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT21__LCDIF_DAT_21 = IOMUX_PAD(0x03FC, 0x00E8, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x00E8, 2,
0x07E0, 1, 0),
@@ -332,7 +332,7 @@ enum {
MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x03FC,
0x00E8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x03FC, 0x00E8, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__MMDC_MMDC_DEBUG_26 = IOMUX_PAD(0x03FC, 0x00E8, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT21__PL301_SIM_MX6DL_PER1_HADDR_29 =
IOMUX_PAD(0x03FC, 0x00E8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__PL301_PER1_HADDR_29 = IOMUX_PAD(0x03FC,
0x00E8, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT22__LCDIF_DAT_22 = IOMUX_PAD(0x0400, 0x00EC, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x00EC, 2,
0x07DC, 1, 0),
@@ -340,7 +340,7 @@ enum {
MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x0400,
0x00EC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x0400, 0x00EC, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__MMDC_MMDC_DEBUG_27 = IOMUX_PAD(0x0400, 0x00EC, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT22__PL301_SIM_MX6DL_PER1_HADDR_30 =
IOMUX_PAD(0x0400, 0x00EC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__PL301_PER1_HADDR_30 = IOMUX_PAD(0x0400,
0x00EC, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT23__LCDIF_DAT_23 = IOMUX_PAD(0x0404, 0x00F0, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x0404, 0x00F0, 2,
0x07E4, 1, 0),
@@ -348,7 +348,7 @@ enum {
MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x0404,
0x00F0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x0404, 0x00F0, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__MMDC_MMDC_DEBUG_28 = IOMUX_PAD(0x0404, 0x00F0, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT23__PL301_SIM_MX6DL_PER1_HADDR_31 =
IOMUX_PAD(0x0404, 0x00F0, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__PL301_PER1_HADDR_31 = IOMUX_PAD(0x0404,
0x00F0, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT3__LCDIF_DAT_3 = IOMUX_PAD(0x0408, 0x00F4, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0408, 0x00F4, 2,
0x0000, 0, 0),
@@ -356,7 +356,7 @@ enum {
MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x0408,
0x00F4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0408, 0x00F4, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__MMDC_MMDC_DEBUG_8 = IOMUX_PAD(0x0408, 0x00F4, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT3__PL301_SIM_MX6DL_PER1_HADDR_14 =
IOMUX_PAD(0x0408, 0x00F4, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__PL301_PER1_HADDR_14 = IOMUX_PAD(0x0408, 0x00F4, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT4__LCDIF_DAT_4 = IOMUX_PAD(0x040C, 0x00F8, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x040C, 0x00F8, 2,
0x0000, 0, 0),
@@ -364,7 +364,7 @@ enum {
MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x040C, 0x00F8, 4,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x040C, 0x00F8, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x040C, 0x00F8, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT4__PL301_SIM_MX6DL_PER1_HADDR_15 =
IOMUX_PAD(0x040C, 0x00F8, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__PL301_PER1_HADDR_15 = IOMUX_PAD(0x040C, 0x00F8, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT5__LCDIF_DAT_5 = IOMUX_PAD(0x0410, 0x00FC, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0410, 0x00FC, 2,
0x0000, 0, 0),
@@ -372,7 +372,7 @@ enum {
MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x0410,
0x00FC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0410, 0x00FC, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__MMDC_MMDC_DEBUG_10 = IOMUX_PAD(0x0410, 0x00FC, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT5__PL301_SIM_MX6DL_PER1_HADDR_16 =
IOMUX_PAD(0x0410, 0x00FC, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__PL301_PER1_HADDR_16 = IOMUX_PAD(0x0410, 0x00FC, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT6__LCDIF_DAT_6 = IOMUX_PAD(0x0414, 0x0100, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x0414, 0x0100, 2,
0x0000, 0, 0),
@@ -380,7 +380,7 @@ enum {
MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x0414,
0x0100, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x0414, 0x0100, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__MMDC_MMDC_DEBUG_11 = IOMUX_PAD(0x0414, 0x0100, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT6__PL301_SIM_MX6DL_PER1_HADDR_17 =
IOMUX_PAD(0x0414, 0x0100, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__PL301_PER1_HADDR_17 = IOMUX_PAD(0x0414, 0x0100, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT7__LCDIF_DAT_7 = IOMUX_PAD(0x0418, 0x0104, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x0418, 0x0104, 2,
0x0000, 0, 0),
@@ -388,7 +388,7 @@ enum {
MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x0418,
0x0104, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x0418, 0x0104, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__MMDC_MMDC_DEBUG_12 = IOMUX_PAD(0x0418, 0x0104, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT7__PL301_SIM_MX6DL_PER1_HADDR_18 =
IOMUX_PAD(0x0418, 0x0104, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__PL301_PER1_HADDR_18 = IOMUX_PAD(0x0418, 0x0104, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT8__LCDIF_DAT_8 = IOMUX_PAD(0x041C, 0x0108, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x041C, 0x0108, 2,
0x0000, 0, 0),
@@ -396,7 +396,7 @@ enum {
MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x041C,
0x0108, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x041C, 0x0108, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__MMDC_MMDC_DEBUG_13 = IOMUX_PAD(0x041C, 0x0108, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT8__PL301_SIM_MX6DL_PER1_HADDR_19 =
IOMUX_PAD(0x041C, 0x0108, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__PL301_PER1_HADDR_19 = IOMUX_PAD(0x041C, 0x0108, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT9__LCDIF_DAT_9 = IOMUX_PAD(0x0420, 0x010C, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x0420, 0x010C, 2,
0x0000, 0, 0),
@@ -404,7 +404,7 @@ enum {
MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x0420,
0x010C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x0420, 0x010C, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__MMDC_MMDC_DEBUG_14 = IOMUX_PAD(0x0420, 0x010C, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT9__PL301_SIM_MX6DL_PER1_HADDR_20 =
IOMUX_PAD(0x0420, 0x010C, 7, 0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__PL301_PER1_HADDR_20 = IOMUX_PAD(0x0420, 0x010C, 7,
0x0000, 0, 0),
MX6_PAD_DRAM_A0__MMDC_DRAM_A_0 = IOMUX_PAD(0x0424, NO_MUX_I,
0, 0x0000, 0, 0),
MX6_PAD_DRAM_A1__MMDC_DRAM_A_1 = IOMUX_PAD(0x0428, NO_MUX_I,
0, 0x0000, 0, 0),
MX6_PAD_DRAM_A10__MMDC_DRAM_A_10 = IOMUX_PAD(0x042C, NO_MUX_I,
0, 0x0000, 0, 0),
@@ -576,7 +576,7 @@ enum {
MX6_PAD_EIM_A23__IPU1_CSI1_D_18 = IOMUX_PAD(0x04FC, 0x012C, 2,
0x08A8, 0, 0),
MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x04FC, 0x012C, 4,
0x0000, 0, 0),
MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x04FC, 0x012C, 5,
0x0000, 0, 0),
- MX6_PAD_EIM_A23__PL301_SIM_MX6DL_PER1_HPROT_3 = IOMUX_PAD(0x04FC,
0x012C, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A23__PL301_PER1_HPROT_3 = IOMUX_PAD(0x04FC, 0x012C, 6,
0x0000, 0, 0),
MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x04FC, 0x012C, 7,
0x0000, 0, 0),
MX6_PAD_EIM_A23__EPDC_GDOE = IOMUX_PAD(0x04FC, 0x012C, 8,
0x0000, 0, 0),
MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x0500, 0x0130, 0,
0x0000, 0, 0),
@@ -584,7 +584,7 @@ enum {
MX6_PAD_EIM_A24__IPU1_CSI1_D_19 = IOMUX_PAD(0x0500, 0x0130, 2,
0x08AC, 0, 0),
MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x0500, 0x0130, 4,
0x0000, 0, 0),
MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x0500, 0x0130, 5,
0x0000, 0, 0),
- MX6_PAD_EIM_A24__PL301_SIM_MX6DL_PER1_HPROT_2 = IOMUX_PAD(0x0500,
0x0130, 6, 0x0000, 0, 0),
+ MX6_PAD_EIM_A24__PL301_PER1_HPROT_2 = IOMUX_PAD(0x0500, 0x0130, 6,
0x0000, 0, 0),
MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x0500, 0x0130, 7,
0x0000, 0, 0),
MX6_PAD_EIM_A24__EPDC_GDRL = IOMUX_PAD(0x0500, 0x0130, 8,
0x0000, 0, 0),
MX6_PAD_EIM_A25__WEIM_WEIM_A_25 = IOMUX_PAD(0x0504, 0x0134, 0,
0x0000, 0, 0),
@@ -594,7 +594,7 @@ enum {
MX6_PAD_EIM_A25__IPU1_DI0_D1_CS = IOMUX_PAD(0x0504, 0x0134, 4,
0x0000, 0, 0),
MX6_PAD_EIM_A25__GPIO_5_2 = IOMUX_PAD(0x0504, 0x0134, 5,
0x0000, 0, 0),
MX6_PAD_EIM_A25__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0504, 0x0134, 6,
0x085C, 0, 0),
- MX6_PAD_EIM_A25__PL301_SIM_MX6DL_PER1_HBURST_0 = IOMUX_PAD(0x0504,
0x0134, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_A25__PL301_PER1_HBURST_0 = IOMUX_PAD(0x0504, 0x0134, 7,
0x0000, 0, 0),
MX6_PAD_EIM_A25__EPDC_SDDO_15 = IOMUX_PAD(0x0504, 0x0134, 8,
0x0000, 0, 0),
MX6_PAD_EIM_A25__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0504, 0x0134, 9,
0x0000, 0, 0),
MX6_PAD_EIM_BCLK__WEIM_WEIM_BCLK = IOMUX_PAD(0x0508, 0x0138, 0,
0x0000, 0, 0),
@@ -632,7 +632,7 @@ enum {
MX6_PAD_EIM_D17__DCIC1_DCIC_OUT = IOMUX_PAD(0x0518, 0x0148, 4,
0x0000, 0, 0),
MX6_PAD_EIM_D17__GPIO_3_17 = IOMUX_PAD(0x0518, 0x0148, 5,
0x0000, 0, 0),
MX6_PAD_EIM_D17__I2C3_SCL = IOMUX_PAD(0x0518, 0x0148, 6 |
IOMUX_CONFIG_SION, 0x0878, 0, 0),
- MX6_PAD_EIM_D17__PL301_SIM_MX6DL_PER1_HBURST_1 = IOMUX_PAD(0x0518,
0x0148, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D17__PL301_PER1_HBURST_1 = IOMUX_PAD(0x0518, 0x0148, 7,
0x0000, 0, 0),
MX6_PAD_EIM_D17__EPDC_VCOM_0 = IOMUX_PAD(0x0518, 0x0148, 8,
0x0000, 0, 0),
MX6_PAD_EIM_D18__WEIM_WEIM_D_18 = IOMUX_PAD(0x051C, 0x014C, 0,
0x0000, 0, 0),
MX6_PAD_EIM_D18__ECSPI1_MOSI = IOMUX_PAD(0x051C, 0x014C, 1,
0x07E0, 2, 0),
@@ -641,7 +641,7 @@ enum {
MX6_PAD_EIM_D18__IPU1_DI1_D0_CS = IOMUX_PAD(0x051C, 0x014C, 4,
0x0000, 0, 0),
MX6_PAD_EIM_D18__GPIO_3_18 = IOMUX_PAD(0x051C, 0x014C, 5,
0x0000, 0, 0),
MX6_PAD_EIM_D18__I2C3_SDA = IOMUX_PAD(0x051C, 0x014C, 6 |
IOMUX_CONFIG_SION, 0x087C, 0, 0),
- MX6_PAD_EIM_D18__PL301_SIM_MX6DL_PER1_HBURST_2 = IOMUX_PAD(0x051C,
0x014C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D18__PL301_PER1_HBURST_2 = IOMUX_PAD(0x051C, 0x014C, 7,
0x0000, 0, 0),
MX6_PAD_EIM_D18__EPDC_VCOM_1 = IOMUX_PAD(0x051C, 0x014C, 8,
0x0000, 0, 0),
MX6_PAD_EIM_D19__WEIM_WEIM_D_19 = IOMUX_PAD(0x0520, 0x0150, 0,
0x0000, 0, 0),
MX6_PAD_EIM_D19__ECSPI1_SS1 = IOMUX_PAD(0x0520, 0x0150, 1,
0x07E8, 1, 0),
@@ -651,7 +651,7 @@ enum {
MX6_PAD_EIM_D19__UART1_RTS = IOMUX_PAD(0x0520, 0x0150, 4,
0x08F8, 0, 0),
MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x0520, 0x0150, 5,
0x0000, 0, 0),
MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x0520, 0x0150, 6,
0x0000, 0, 0),
- MX6_PAD_EIM_D19__PL301_SIM_MX6DL_PER1_HRESP = IOMUX_PAD(0x0520,
0x0150, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D19__PL301_PER1_HRESP = IOMUX_PAD(0x0520, 0x0150, 7,
0x0000, 0, 0),
MX6_PAD_EIM_D19__EPDC_SDDO_12 = IOMUX_PAD(0x0520, 0x0150, 8,
0x0000, 0, 0),
MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x0524, 0x0154, 0,
0x0000, 0, 0),
MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x0524, 0x0154, 1,
0x0808, 0, 0),
@@ -677,7 +677,7 @@ enum {
MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x052C, 0x015C, 4,
0x0000, 0, 0),
MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x052C, 0x015C, 5,
0x0000, 0, 0),
MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x052C, 0x015C, 6,
0x0000, 0, 0),
- MX6_PAD_EIM_D22__PL301_SIM_MX6DL_PER1_HWRITE = IOMUX_PAD(0x052C,
0x015C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D22__PL301_PER1_HWRITE = IOMUX_PAD(0x052C, 0x015C, 7,
0x0000, 0, 0),
MX6_PAD_EIM_D22__EPDC_SDCE_6 = IOMUX_PAD(0x052C, 0x015C, 8,
0x0000, 0, 0),
MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x0530, 0x0160, 0,
0x0000, 0, 0),
MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x0530, 0x0160, 1,
0x0000, 0, 0),
@@ -756,7 +756,7 @@ enum {
MX6_PAD_EIM_D30__UART3_RTS = IOMUX_PAD(0x054C, 0x017C, 4,
0x0908, 1, 0),
MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x054C, 0x017C, 5,
0x0000, 0, 0),
MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x054C, 0x017C, 6,
0x0924, 0, 0),
- MX6_PAD_EIM_D30__PL301_SIM_MX6DL_PER1_HPROT_0 = IOMUX_PAD(0x054C,
0x017C, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D30__PL301_PER1_HPROT_0 = IOMUX_PAD(0x054C, 0x017C, 7,
0x0000, 0, 0),
MX6_PAD_EIM_D30__EPDC_SDOEZ = IOMUX_PAD(0x054C, 0x017C, 8,
0x0000, 0, 0),
MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x0550, 0x0180, 0,
0x0000, 0, 0),
MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x0550, 0x0180, 1,
0x0000, 0, 0),
@@ -766,7 +766,7 @@ enum {
MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x0550, 0x0180, 4,
0x0908, 2, 0),
MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x0550, 0x0180, 5,
0x0000, 0, 0),
MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x0550, 0x0180, 6,
0x0000, 0, 0),
- MX6_PAD_EIM_D31__PL301_SIM_MX6DL_PER1_HPROT_1 = IOMUX_PAD(0x0550,
0x0180, 7, 0x0000, 0, 0),
+ MX6_PAD_EIM_D31__PL301_PER1_HPROT_1 = IOMUX_PAD(0x0550, 0x0180, 7,
0x0000, 0, 0),
MX6_PAD_EIM_D31__EPDC_SDCLK = IOMUX_PAD(0x0550, 0x0180, 8,
0x0000, 0, 0),
MX6_PAD_EIM_D31__WEIM_ACLK_FREERUN = IOMUX_PAD(0x0550, 0x0180, 9,
0x0000, 0, 0),
MX6_PAD_EIM_DA0__WEIM_WEIM_DA_A_0 = IOMUX_PAD(0x0554, 0x0184, 0,
0x0000, 0, 0),
@@ -1169,7 +1169,7 @@ enum {
MX6_PAD_KEY_COL1__UART5_RXD = IOMUX_PAD(0x0630, 0x0248, 4,
0x091C, 2, 0),
MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x0630, 0x0248, 5,
0x0000, 0, 0),
MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x0630, 0x0248, 6,
0x0000, 0, 0),
- MX6_PAD_KEY_COL1__PL301_SIM_MX6DL_PER1_HADDR_1 = IOMUX_PAD(0x0630,
0x0248, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__PL301_PER1_HADDR_1 = IOMUX_PAD(0x0630, 0x0248, 7,
0x0000, 0, 0),
MX6_PAD_KEY_COL2__ECSPI1_SS1 = IOMUX_PAD(0x0634, 0x024C, 0,
0x07E8, 2, 0),
MX6_PAD_KEY_COL2__ENET_RDATA_2 = IOMUX_PAD(0x0634, 0x024C, 1,
0x0820, 0, 0),
MX6_PAD_KEY_COL2__CAN1_TXCAN = IOMUX_PAD(0x0634, 0x024C, 2,
0x0000, 0, 0),
@@ -1177,7 +1177,7 @@ enum {
MX6_PAD_KEY_COL2__ENET_MDC = IOMUX_PAD(0x0634, 0x024C, 4,
0x0000, 0, 0),
MX6_PAD_KEY_COL2__GPIO_4_10 = IOMUX_PAD(0x0634, 0x024C, 5,
0x0000, 0, 0),
MX6_PAD_KEY_COL2__USBOH3_H1USB_PWRCTL_WAKEUP = IOMUX_PAD(0x0634,
0x024C, 6, 0x0000, 0, 0),
- MX6_PAD_KEY_COL2__PL301_SIM_MX6DL_PER1_HADDR_3 = IOMUX_PAD(0x0634,
0x024C, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL2__PL301_PER1_HADDR_3 = IOMUX_PAD(0x0634, 0x024C, 7,
0x0000, 0, 0),
MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x0638, 0x0250, 0,
0x07F0, 1, 0),
MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x0638, 0x0250, 1,
0x0000, 0, 0),
MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x0638, 0x0250, 2,
0x0860, 1, 0),
@@ -1185,7 +1185,7 @@ enum {
MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x0638, 0x0250, 4 |
IOMUX_CONFIG_SION, 0x0870, 1, 0),
MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x0638, 0x0250, 5,
0x0000, 0, 0),
MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x0638, 0x0250, 6,
0x08F0, 3, 0),
- MX6_PAD_KEY_COL3__PL301_SIM_MX6DL_PER1_HADDR_5 = IOMUX_PAD(0x0638,
0x0250, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__PL301_PER1_HADDR_5 = IOMUX_PAD(0x0638, 0x0250, 7,
0x0000, 0, 0),
MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x063C, 0x0254, 0,
0x0000, 0, 0),
MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x063C, 0x0254, 1,
0x0000, 0, 0),
MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x063C, 0x0254, 2,
0x0920, 1, 0),
@@ -1194,7 +1194,7 @@ enum {
MX6_PAD_KEY_COL4__UART5_RTS = IOMUX_PAD(0x063C, 0x0254, 4,
0x0918, 2, 0),
MX6_PAD_KEY_COL4__GPIO_4_14 = IOMUX_PAD(0x063C, 0x0254, 5,
0x0000, 0, 0),
MX6_PAD_KEY_COL4__MMDC_MMDC_DEBUG_49 = IOMUX_PAD(0x063C, 0x0254, 6,
0x0000, 0, 0),
- MX6_PAD_KEY_COL4__PL301_SIM_MX6DL_PER1_HADDR_7 = IOMUX_PAD(0x063C,
0x0254, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_COL4__PL301_PER1_HADDR_7 = IOMUX_PAD(0x063C, 0x0254, 7,
0x0000, 0, 0),
MX6_PAD_KEY_ROW0__ECSPI1_MOSI = IOMUX_PAD(0x0640, 0x0258, 0,
0x07E0, 3, 0),
MX6_PAD_KEY_ROW0__ENET_TDATA_3 = IOMUX_PAD(0x0640, 0x0258, 1,
0x0000, 0, 0),
MX6_PAD_KEY_ROW0__AUDMUX_AUD5_TXD = IOMUX_PAD(0x0640, 0x0258, 2,
0x07B4, 1, 0),
@@ -1203,7 +1203,7 @@ enum {
MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x0640, 0x0258, 4,
0x0914, 3, 0),
MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x0640, 0x0258, 5,
0x0000, 0, 0),
MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x0640, 0x0258, 6,
0x0000, 0, 0),
- MX6_PAD_KEY_ROW0__PL301_SIM_MX6DL_PER1_HADDR_0 = IOMUX_PAD(0x0640,
0x0258, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__PL301_PER1_HADDR_0 = IOMUX_PAD(0x0640, 0x0258, 7,
0x0000, 0, 0),
MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x0644, 0x025C, 0,
0x07E4, 3, 0),
MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x0644, 0x025C, 1,
0x0000, 0, 0),
MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x0644, 0x025C, 2,
0x07B0, 1, 0),
@@ -1212,7 +1212,7 @@ enum {
MX6_PAD_KEY_ROW1__UART5_RXD = IOMUX_PAD(0x0644, 0x025C, 4,
0x091C, 3, 0),
MX6_PAD_KEY_ROW1__GPIO_4_9 = IOMUX_PAD(0x0644, 0x025C, 5,
0x0000, 0, 0),
MX6_PAD_KEY_ROW1__USDHC2_VSELECT = IOMUX_PAD(0x0644, 0x025C, 6,
0x0000, 0, 0),
- MX6_PAD_KEY_ROW1__PL301_SIM_MX6DL_PER1_HADDR_2 = IOMUX_PAD(0x0644,
0x025C, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW1__PL301_PER1_HADDR_2 = IOMUX_PAD(0x0644, 0x025C, 7,
0x0000, 0, 0),
MX6_PAD_KEY_ROW2__ECSPI1_SS2 = IOMUX_PAD(0x0648, 0x0260, 0,
0x07EC, 1, 0),
MX6_PAD_KEY_ROW2__ENET_TDATA_2 = IOMUX_PAD(0x0648, 0x0260, 1,
0x0000, 0, 0),
MX6_PAD_KEY_ROW2__CAN1_RXCAN = IOMUX_PAD(0x0648, 0x0260, 2,
0x07C8, 1, 0),
@@ -1220,7 +1220,7 @@ enum {
MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x0648, 0x0260, 4,
0x0000, 0, 0),
MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x0648, 0x0260, 5,
0x0000, 0, 0),
MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x0648, 0x0260, 6,
0x085C, 1, 0),
- MX6_PAD_KEY_ROW2__PL301_SIM_MX6DL_PER1_HADDR_4 = IOMUX_PAD(0x0648,
0x0260, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__PL301_PER1_HADDR_4 = IOMUX_PAD(0x0648, 0x0260, 7,
0x0000, 0, 0),
MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x064C, 0x0264, 0,
0x0000, 0, 0),
MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x064C, 0x0264, 1,
0x0794, 2, 0),
MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x064C, 0x0264, 2,
0x0864, 1, 0),
@@ -1228,7 +1228,7 @@ enum {
MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x064C, 0x0264, 4 |
IOMUX_CONFIG_SION, 0x0874, 1, 0),
MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x064C, 0x0264, 5,
0x0000, 0, 0),
MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x064C, 0x0264, 6,
0x0000, 0, 0),
- MX6_PAD_KEY_ROW3__PL301_SIM_MX6DL_PER1_HADDR_6 = IOMUX_PAD(0x064C,
0x0264, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__PL301_PER1_HADDR_6 = IOMUX_PAD(0x064C, 0x0264, 7,
0x0000, 0, 0),
MX6_PAD_KEY_ROW4__CAN2_RXCAN = IOMUX_PAD(0x0650, 0x0268, 0,
0x07CC, 0, 0),
MX6_PAD_KEY_ROW4__IPU1_SISG_5 = IOMUX_PAD(0x0650, 0x0268, 1,
0x0000, 0, 0),
MX6_PAD_KEY_ROW4__USBOH3_USBOTG_PWR = IOMUX_PAD(0x0650, 0x0268, 2,
0x0000, 0, 0),
@@ -1237,7 +1237,7 @@ enum {
MX6_PAD_KEY_ROW4__UART5_RTS = IOMUX_PAD(0x0650, 0x0268, 4,
0x0918, 3, 0),
MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x0650, 0x0268, 5,
0x0000, 0, 0),
MX6_PAD_KEY_ROW4__MMDC_MMDC_DEBUG_50 = IOMUX_PAD(0x0650, 0x0268, 6,
0x0000, 0, 0),
- MX6_PAD_KEY_ROW4__PL301_SIM_MX6DL_PER1_HADDR_8 = IOMUX_PAD(0x0650,
0x0268, 7, 0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__PL301_PER1_HADDR_8 = IOMUX_PAD(0x0650, 0x0268, 7,
0x0000, 0, 0),
MX6_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK = IOMUX_PAD(NO_PAD_I, NO_MUX_I,
0, 0x0000, 0, 0),
MX6_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 = IOMUX_PAD(NO_PAD_I, NO_MUX_I,
0, 0x0000, 0, 0),
MX6_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 = IOMUX_PAD(NO_PAD_I, NO_MUX_I,
0, 0x0000, 0, 0),
@@ -1273,7 +1273,7 @@ enum {
MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x0660, 0x0278, 2,
0x0000, 0, 0),
MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 =
IOMUX_PAD(0x0660, 0x0278, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x0660, 0x0278, 5,
0x0000, 0, 0),
- MX6_PAD_NANDF_CS1__PL301_SIM_MX6DL_PER1_HREADYOUT =
IOMUX_PAD(0x0660, 0x0278, 7, 0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__PL301_PER1_HREADYOUT = IOMUX_PAD(0x0660, 0x0278, 7,
0x0000, 0, 0),
MX6_PAD_NANDF_CS1__USDHC1_CLKI = IOMUX_PAD(0x0660, 0x0278, 8,
0x0928, 0, 0),
MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x0664, 0x027C, 0,
0x0000, 0, 0),
MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x0664, 0x027C, 1,
0x0000, 0, 0),
diff --git a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
index 798629a..78b33ba 100644
--- a/arch/arm/include/asm/arch-mx6/mx6q_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q_pins.h
@@ -135,7 +135,7 @@ enum {
MX6_PAD_EIM_D19__UART1_CTS = IOMUX_PAD(0x03B0, 0x009C, 4,
0x091C, 0, 0),
MX6_PAD_EIM_D19__GPIO_3_19 = IOMUX_PAD(0x03B0, 0x009C, 5,
0x0000, 0, 0),
MX6_PAD_EIM_D19__EPIT1_EPITO = IOMUX_PAD(0x03B0, 0x009C, 6,
0x0000, 0, 0),
- MX6_PAD_EIM_D19__PL301MX6QPER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7,
0x0000, 0, 0),
+ MX6_PAD_EIM_D19__PL301_PER1_HRESP = IOMUX_PAD(0x03B0, 0x009C, 7,
0x0000, 0, 0),
MX6_PAD_EIM_D20__WEIM_WEIM_D_20 = IOMUX_PAD(0x03B4, 0x00A0, 0, 0x0000,
0, 0),
MX6_PAD_EIM_D20__ECSPI4_SS0 = IOMUX_PAD(0x03B4, 0x00A0, 1,
0x0824, 0, 0),
MX6_PAD_EIM_D20__IPU1_DI0_PIN16 = IOMUX_PAD(0x03B4, 0x00A0, 2, 0x0000,
0, 0),
@@ -159,7 +159,7 @@ enum {
MX6_PAD_EIM_D22__USBOH3_USBOTG_PWR = IOMUX_PAD(0x03BC, 0x00A8, 4,
0x0000, 0, 0),
MX6_PAD_EIM_D22__GPIO_3_22 = IOMUX_PAD(0x03BC, 0x00A8, 5,
0x0000, 0, 0),
MX6_PAD_EIM_D22__SPDIF_OUT1 = IOMUX_PAD(0x03BC, 0x00A8, 6,
0x0000, 0, 0),
- MX6_PAD_EIM_D22__PL301MX6QPER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7,
0x0000, 0, 0),
+ MX6_PAD_EIM_D22__PL301_PER1_HWRITE = IOMUX_PAD(0x03BC, 0x00A8, 7,
0x0000, 0, 0),
MX6_PAD_EIM_D23__WEIM_WEIM_D_23 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000,
0, 0),
MX6_PAD_EIM_D23__IPU1_DI0_D0_CS = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x0000,
0, 0),
MX6_PAD_EIM_D23__UART3_CTS = IOMUX_PAD(0x03C0, 0x00AC, 2,
0x092C, 0, 0),
@@ -234,7 +234,7 @@ enum {
MX6_PAD_EIM_D30__UART3_CTS = IOMUX_PAD(0x03E0, 0x00CC, 4,
0x092C, 2, 0),
MX6_PAD_EIM_D30__GPIO_3_30 = IOMUX_PAD(0x03E0, 0x00CC, 5,
0x0000, 0, 0),
MX6_PAD_EIM_D30__USBOH3_USBH1_OC = IOMUX_PAD(0x03E0, 0x00CC, 6,
0x0948, 0, 0),
- MX6_PAD_EIM_D30__PL301MX6QPER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7,
0x0000, 0, 0),
+ MX6_PAD_EIM_D30__PL301_PER1_HPROT_0 = IOMUX_PAD(0x03E0, 0x00CC, 7,
0x0000, 0, 0),
MX6_PAD_EIM_D31__WEIM_WEIM_D_31 = IOMUX_PAD(0x03E4, 0x00D0, 0, 0x0000,
0, 0),
MX6_PAD_EIM_D31__IPU1_DISP1_DAT_20 = IOMUX_PAD(0x03E4, 0x00D0, 1,
0x0000, 0, 0),
MX6_PAD_EIM_D31__IPU1_DI0_PIN12 = IOMUX_PAD(0x03E4, 0x00D0, 2, 0x0000,
0, 0),
@@ -243,14 +243,14 @@ enum {
MX6_PAD_EIM_D31__UART3_RTS = IOMUX_PAD(0x03E4, 0x00D0, 4,
0x092C, 3, 0),
MX6_PAD_EIM_D31__GPIO_3_31 = IOMUX_PAD(0x03E4, 0x00D0, 5,
0x0000, 0, 0),
MX6_PAD_EIM_D31__USBOH3_USBH1_PWR = IOMUX_PAD(0x03E4, 0x00D0, 6,
0x0000, 0, 0),
- MX6_PAD_EIM_D31__PL301MX6QPER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7,
0x0000, 0, 0),
+ MX6_PAD_EIM_D31__PL301_PER1_HPROT_1 = IOMUX_PAD(0x03E4, 0x00D0, 7,
0x0000, 0, 0),
MX6_PAD_EIM_A24__WEIM_WEIM_A_24 = IOMUX_PAD(0x03E8, 0x00D4, 0, 0x0000,
0, 0),
MX6_PAD_EIM_A24__IPU1_DISP1_DAT_19 = IOMUX_PAD(0x03E8, 0x00D4, 1,
0x0000, 0, 0),
MX6_PAD_EIM_A24__IPU2_CSI1_D_19 = IOMUX_PAD(0x03E8, 0x00D4, 2, 0x08D4,
1, 0),
MX6_PAD_EIM_A24__IPU2_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 3,
0x0000, 0, 0),
MX6_PAD_EIM_A24__IPU1_SISG_2 = IOMUX_PAD(0x03E8, 0x00D4, 4,
0x0000, 0, 0),
MX6_PAD_EIM_A24__GPIO_5_4 = IOMUX_PAD(0x03E8, 0x00D4, 5,
0x0000, 0, 0),
- MX6_PAD_EIM_A24__PL301MX6QPER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6,
0x0000, 0, 0),
+ MX6_PAD_EIM_A24__PL301_PER1_HPROT_2 = IOMUX_PAD(0x03E8, 0x00D4, 6,
0x0000, 0, 0),
MX6_PAD_EIM_A24__SRC_BT_CFG_24 = IOMUX_PAD(0x03E8, 0x00D4, 7,
0x0000, 0, 0),
MX6_PAD_EIM_A23__WEIM_WEIM_A_23 = IOMUX_PAD(0x03EC, 0x00D8, 0, 0x0000,
0, 0),
MX6_PAD_EIM_A23__IPU1_DISP1_DAT_18 = IOMUX_PAD(0x03EC, 0x00D8, 1,
0x0000, 0, 0),
@@ -258,7 +258,7 @@ enum {
MX6_PAD_EIM_A23__IPU2_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 3,
0x0000, 0, 0),
MX6_PAD_EIM_A23__IPU1_SISG_3 = IOMUX_PAD(0x03EC, 0x00D8, 4,
0x0000, 0, 0),
MX6_PAD_EIM_A23__GPIO_6_6 = IOMUX_PAD(0x03EC, 0x00D8, 5,
0x0000, 0, 0),
- MX6_PAD_EIM_A23__PL301MX6QPER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6,
0x0000, 0, 0),
+ MX6_PAD_EIM_A23__PL301_PER1_HPROT_3 = IOMUX_PAD(0x03EC, 0x00D8, 6,
0x0000, 0, 0),
MX6_PAD_EIM_A23__SRC_BT_CFG_23 = IOMUX_PAD(0x03EC, 0x00D8, 7,
0x0000, 0, 0),
MX6_PAD_EIM_A22__WEIM_WEIM_A_22 = IOMUX_PAD(0x03F0, 0x00DC, 0, 0x0000,
0, 0),
MX6_PAD_EIM_A22__IPU1_DISP1_DAT_17 = IOMUX_PAD(0x03F0, 0x00DC, 1,
0x0000, 0, 0),
@@ -541,7 +541,7 @@ enum {
MX6_PAD_DISP0_DAT1__SDMA_DEBUG_EVENT_CHANNEL_SEL = IOMUX_PAD(0x0488,
0x0174, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__GPIO_4_22 = IOMUX_PAD(0x0488, 0x0174, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT1__MMDC_DEBUG_6 = IOMUX_PAD(0x0488, 0x0174, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT1__PL301_PER1_HADR_12 = IOMUX_PAD(0x0488, 0x0174, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT1__PL301_PER1_HADDR_12 = IOMUX_PAD(0x0488, 0x0174, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT2__IPU2_DISP0_DAT_2 = IOMUX_PAD(0x048C, 0x0178, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__ECSPI3_MISO = IOMUX_PAD(0x048C, 0x0178, 2, 0x0000,
0, 0),
@@ -549,7 +549,7 @@ enum {
MX6_PAD_DISP0_DAT2__SDMA_DEBUG_MODE = IOMUX_PAD(0x048C, 0x0178, 4,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__GPIO_4_23 = IOMUX_PAD(0x048C, 0x0178, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT2__MMDC_DEBUG_7 = IOMUX_PAD(0x048C, 0x0178, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT2__PL301_PER1_HADR_13 = IOMUX_PAD(0x048C, 0x0178, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT2__PL301_PER1_HADDR_13 = IOMUX_PAD(0x048C, 0x0178, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT3__IPU2_DISP0_DAT_3 = IOMUX_PAD(0x0490, 0x017C, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__ECSPI3_SS0 = IOMUX_PAD(0x0490, 0x017C, 2,
0x0000, 0, 0),
@@ -557,7 +557,7 @@ enum {
MX6_PAD_DISP0_DAT3__SDMA_DEBUG_BUS_ERROR = IOMUX_PAD(0x0490, 0x017C, 4,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__GPIO_4_24 = IOMUX_PAD(0x0490, 0x017C, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT3__MMDC_MMDC_DBG_8 = IOMUX_PAD(0x0490, 0x017C, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT3__PL301_PER1_HADR_14 = IOMUX_PAD(0x0490, 0x017C, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT3__PL301_PER1_HADDR_14 = IOMUX_PAD(0x0490, 0x017C, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT4__IPU2_DISP0_DAT_4 = IOMUX_PAD(0x0494, 0x0180, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__ECSPI3_SS1 = IOMUX_PAD(0x0494, 0x0180, 2,
0x0000, 0, 0),
@@ -565,7 +565,7 @@ enum {
MX6_PAD_DISP0_DAT4__SDMA_DEBUG_BUS_RWB = IOMUX_PAD(0x0494, 0x0180, 4,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__GPIO_4_25 = IOMUX_PAD(0x0494, 0x0180, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT4__MMDC_MMDC_DEBUG_9 = IOMUX_PAD(0x0494, 0x0180, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT4__PL301_PER1_HADR_15 = IOMUX_PAD(0x0494, 0x0180, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT4__PL301_PER1_HADDR_15 = IOMUX_PAD(0x0494, 0x0180, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT5__IPU2_DISP0_DAT_5 = IOMUX_PAD(0x0498, 0x0184, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__ECSPI3_SS2 = IOMUX_PAD(0x0498, 0x0184, 2,
0x0000, 0, 0),
@@ -573,7 +573,7 @@ enum {
MX6_PAD_DISP0_DAT5__SDMA_DEBUG_MATCHED_DMBUS = IOMUX_PAD(0x0498,
0x0184, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__GPIO_4_26 = IOMUX_PAD(0x0498, 0x0184, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT5__MMDC_DEBUG_10 = IOMUX_PAD(0x0498, 0x0184, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT5__PL301_PER1_HADR_16 = IOMUX_PAD(0x0498, 0x0184, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT5__PL301_PER1_HADDR_16 = IOMUX_PAD(0x0498, 0x0184, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT6__IPU2_DISP0_DAT_6 = IOMUX_PAD(0x049C, 0x0188, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__ECSPI3_SS3 = IOMUX_PAD(0x049C, 0x0188, 2,
0x0000, 0, 0),
@@ -581,7 +581,7 @@ enum {
MX6_PAD_DISP0_DAT6__SDMA_DEBUG_RTBUFFER_WRITE = IOMUX_PAD(0x049C,
0x0188, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__GPIO_4_27 = IOMUX_PAD(0x049C, 0x0188, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT6__MMDC_DEBUG_11 = IOMUX_PAD(0x049C, 0x0188, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT6__PL301_PER1_HADR_17 = IOMUX_PAD(0x049C, 0x0188, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT6__PL301_PER1_HADDR_17 = IOMUX_PAD(0x049C, 0x0188, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT7__IPU2_DISP0_DAT_7 = IOMUX_PAD(0x04A0, 0x018C, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__ECSPI3_RDY = IOMUX_PAD(0x04A0, 0x018C, 2,
0x0000, 0, 0),
@@ -589,7 +589,7 @@ enum {
MX6_PAD_DISP0_DAT7__SDMA_DEBUG_EVENT_CHANNEL_0 = IOMUX_PAD(0x04A0,
0x018C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__GPIO_4_28 = IOMUX_PAD(0x04A0, 0x018C, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT7__MMDC_DEBUG_12 = IOMUX_PAD(0x04A0, 0x018C, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT7__PL301_PER1_HADR_18 = IOMUX_PAD(0x04A0, 0x018C, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT7__PL301_PER1_HADDR_18 = IOMUX_PAD(0x04A0, 0x018C, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT8__IPU2_DISP0_DAT_8 = IOMUX_PAD(0x04A4, 0x0190, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__PWM1_PWMO = IOMUX_PAD(0x04A4, 0x0190, 2,
0x0000, 0, 0),
@@ -597,7 +597,7 @@ enum {
MX6_PAD_DISP0_DAT8__SDMA_DEBUG_EVENT_CHANNEL_1 = IOMUX_PAD(0x04A4,
0x0190, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__GPIO_4_29 = IOMUX_PAD(0x04A4, 0x0190, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT8__MMDC_DEBUG_13 = IOMUX_PAD(0x04A4, 0x0190, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT8__PL301_PER1_HADR_19 = IOMUX_PAD(0x04A4, 0x0190, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT8__PL301_PER1_HADDR_19 = IOMUX_PAD(0x04A4, 0x0190, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT9__IPU2_DISP0_DAT_9 = IOMUX_PAD(0x04A8, 0x0194, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__PWM2_PWMO = IOMUX_PAD(0x04A8, 0x0194, 2,
0x0000, 0, 0),
@@ -605,35 +605,35 @@ enum {
MX6_PAD_DISP0_DAT9__SDMA_DEBUG_EVENT_CHANNEL_2 = IOMUX_PAD(0x04A8,
0x0194, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__GPIO_4_30 = IOMUX_PAD(0x04A8, 0x0194, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT9__MMDC_DEBUG_14 = IOMUX_PAD(0x04A8, 0x0194, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT9__PL301_PER1_HADR_20 = IOMUX_PAD(0x04A8, 0x0194, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT9__PL301_PER1_HADDR_20 = IOMUX_PAD(0x04A8, 0x0194, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT10__IPU2_DISP0_DAT_10 = IOMUX_PAD(0x04AC, 0x0198, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__USDHC1_DBG_6 = IOMUX_PAD(0x04AC, 0x0198, 3,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__SDMA_DEBUG_EVENT_CHANNEL_3 = IOMUX_PAD(0x04AC,
0x0198, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__GPIO_4_31 = IOMUX_PAD(0x04AC, 0x0198, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT10__MMDC_DEBUG_15 = IOMUX_PAD(0x04AC, 0x0198, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT10__PL301_PER1_HADR21 = IOMUX_PAD(0x04AC, 0x0198, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT10__PL301_PER1_HADDR_21 = IOMUX_PAD(0x04AC, 0x0198, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT11__IPU2_DISP0_DAT_11 = IOMUX_PAD(0x04B0, 0x019C, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__USDHC1_USDHC_DBG7 = IOMUX_PAD(0x04B0, 0x019C, 3,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x04B0,
0x019C, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__GPIO_5_5 = IOMUX_PAD(0x04B0, 0x019C, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT11__MMDC_DEBUG_16 = IOMUX_PAD(0x04B0, 0x019C, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT11__PL301_PER1_HADR22 = IOMUX_PAD(0x04B0, 0x019C, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT11__PL301_PER1_HADDR_22 = IOMUX_PAD(0x04B0, 0x019C, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT12__IPU2_DISP0_DAT_12 = IOMUX_PAD(0x04B4, 0x01A0, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__RESERVED_RESERVED = IOMUX_PAD(0x04B4, 0x01A0, 3,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__SDMA_DEBUG_EVENT_CHANNEL_5 = IOMUX_PAD(0x04B4,
0x01A0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__GPIO_5_6 = IOMUX_PAD(0x04B4, 0x01A0, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT12__MMDC_DEBUG_17 = IOMUX_PAD(0x04B4, 0x01A0, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT12__PL301_PER1_HADR23 = IOMUX_PAD(0x04B4, 0x01A0, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT12__PL301_PER1_HADDR_23 = IOMUX_PAD(0x04B4, 0x01A0, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT13__IPU2_DISP0_DAT_13 = IOMUX_PAD(0x04B8, 0x01A4, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x04B8, 0x01A4, 3,
0x07D8, 1, 0),
MX6_PAD_DISP0_DAT13__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x04B8,
0x01A4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__GPIO_5_7 = IOMUX_PAD(0x04B8, 0x01A4, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT13__MMDC_DEBUG_18 = IOMUX_PAD(0x04B8, 0x01A4, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT13__PL301_PER1_HADR24 = IOMUX_PAD(0x04B8, 0x01A4, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT13__PL301_PER1_HADDR_24 = IOMUX_PAD(0x04B8, 0x01A4, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT14__IPU2_DISP0_DAT_14 = IOMUX_PAD(0x04BC, 0x01A8, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT14__AUDMUX_AUD5_RXC = IOMUX_PAD(0x04BC, 0x01A8, 3,
0x07D4, 1, 0),
@@ -647,7 +647,7 @@ enum {
MX6_PAD_DISP0_DAT15__SDMA_DEBUG_EVT_CHN_LINES_2 = IOMUX_PAD(0x04C0,
0x01AC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__GPIO_5_9 = IOMUX_PAD(0x04C0, 0x01AC, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT15__MMDC_DEBUG_20 = IOMUX_PAD(0x04C0, 0x01AC, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT15__PL301_PER1_HADR25 = IOMUX_PAD(0x04C0, 0x01AC, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT15__PL301_PER1_HADDR_25 = IOMUX_PAD(0x04C0, 0x01AC, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT16__IPU2_DISP0_DAT_16 = IOMUX_PAD(0x04C4, 0x01B0, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__ECSPI2_MOSI = IOMUX_PAD(0x04C4, 0x01B0, 2,
0x0818, 1, 0),
@@ -655,7 +655,7 @@ enum {
MX6_PAD_DISP0_DAT16__SDMA_SDMA_EXT_EVENT_0 = IOMUX_PAD(0x04C4,
0x01B0, 4, 0x090C, 0, 0),
MX6_PAD_DISP0_DAT16__GPIO_5_10 = IOMUX_PAD(0x04C4, 0x01B0, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT16__MMDC_DEBUG_21 = IOMUX_PAD(0x04C4, 0x01B0, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT16__PL301_PER1_HADR26 = IOMUX_PAD(0x04C4, 0x01B0, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT16__PL301_PER1_HADDR_26 = IOMUX_PAD(0x04C4, 0x01B0, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT17__IPU2_DISP0_DAT_17 = IOMUX_PAD(0x04C8, 0x01B4, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__ECSPI2_MISO = IOMUX_PAD(0x04C8, 0x01B4, 2,
0x0814, 1, 0),
@@ -663,7 +663,7 @@ enum {
MX6_PAD_DISP0_DAT17__SDMA_SDMA_EXT_EVENT_1 = IOMUX_PAD(0x04C8,
0x01B4, 4, 0x0910, 0, 0),
MX6_PAD_DISP0_DAT17__GPIO_5_11 = IOMUX_PAD(0x04C8, 0x01B4, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT17__MMDC_DEBUG_22 = IOMUX_PAD(0x04C8, 0x01B4, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT17__PL301_PER1_HADR27 = IOMUX_PAD(0x04C8, 0x01B4, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT17__PL301_PER1_HADDR_27 = IOMUX_PAD(0x04C8,
0x01B4, 7, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT18__IPU2_DISP0_DAT_18 = IOMUX_PAD(0x04CC, 0x01B8, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT18__ECSPI2_SS0 = IOMUX_PAD(0x04CC, 0x01B8, 2, 0x081C,
1, 0),
@@ -687,7 +687,7 @@ enum {
MX6_PAD_DISP0_DAT20__SDMA_DEBUG_EVT_CHN_LINES_7 = IOMUX_PAD(0x04D4,
0x01C0, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__GPIO_5_14 = IOMUX_PAD(0x04D4, 0x01C0, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT20__MMDC_DEBUG_25 = IOMUX_PAD(0x04D4, 0x01C0, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT20__PL301_PER1_HADR28 = IOMUX_PAD(0x04D4, 0x01C0, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT20__PL301_PER1_HADDR_28 = IOMUX_PAD(0x04D4, 0x01C0, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT21__IPU2_DISP0_DAT_21 = IOMUX_PAD(0x04D8, 0x01C4, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__ECSPI1_MOSI = IOMUX_PAD(0x04D8, 0x01C4, 2,
0x07FC, 1, 0),
@@ -695,7 +695,7 @@ enum {
MX6_PAD_DISP0_DAT21__SDMA_DEBUG_BUS_DEVICE_0 = IOMUX_PAD(0x04D8,
0x01C4, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__GPIO_5_15 = IOMUX_PAD(0x04D8, 0x01C4, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT21__MMDC_DEBUG_26 = IOMUX_PAD(0x04D8, 0x01C4, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT21__PL301_PER1_HADR29 = IOMUX_PAD(0x04D8, 0x01C4, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT21__PL301_PER1_HADDR_29 = IOMUX_PAD(0x04D8, 0x01C4, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT22__IPU2_DISP0_DAT_22 = IOMUX_PAD(0x04DC, 0x01C8, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__ECSPI1_MISO = IOMUX_PAD(0x04DC, 0x01C8, 2,
0x07F8, 1, 0),
@@ -703,7 +703,7 @@ enum {
MX6_PAD_DISP0_DAT22__SDMA_DEBUG_BUS_DEVICE_1 = IOMUX_PAD(0x04DC,
0x01C8, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__GPIO_5_16 = IOMUX_PAD(0x04DC, 0x01C8, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT22__MMDC_DEBUG_27 = IOMUX_PAD(0x04DC, 0x01C8, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT22__PL301_PER1_HADR30 = IOMUX_PAD(0x04DC, 0x01C8, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT22__PL301_PER1_HADDR_30 = IOMUX_PAD(0x04DC, 0x01C8, 7,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 0,
0x0000, 0, PAD_CTL_DSE_120ohm),
MX6_PAD_DISP0_DAT23__IPU2_DISP0_DAT_23 = IOMUX_PAD(0x04E0, 0x01CC, 1,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__ECSPI1_SS0 = IOMUX_PAD(0x04E0, 0x01CC, 2, 0x0800,
1, 0),
@@ -711,7 +711,7 @@ enum {
MX6_PAD_DISP0_DAT23__SDMA_DEBUG_BUS_DEVICE_2 = IOMUX_PAD(0x04E0,
0x01CC, 4, 0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__GPIO_5_17 = IOMUX_PAD(0x04E0, 0x01CC, 5,
0x0000, 0, 0),
MX6_PAD_DISP0_DAT23__MMDC_DEBUG_28 = IOMUX_PAD(0x04E0, 0x01CC, 6,
0x0000, 0, 0),
- MX6_PAD_DISP0_DAT23__PL301_PER1_HADR31 = IOMUX_PAD(0x04E0, 0x01CC, 7,
0x0000, 0, 0),
+ MX6_PAD_DISP0_DAT23__PL301_PER1_HADDR_31 = IOMUX_PAD(0x04E0,
0x01CC, 7, 0x0000, 0, 0),
MX6_PAD_ENET_MDIO__RESERVED_RESERVED = IOMUX_PAD(0x04E4, 0x01D0, 0,
0x0000, 0, 0),
MX6_PAD_ENET_MDIO__ENET_MDIO = IOMUX_PAD(0x04E4, 0x01D0, 1,
0x0840, 0, 0),
MX6_PAD_ENET_MDIO__ESAI1_SCKR = IOMUX_PAD(0x04E4, 0x01D0, 2,
0x086C, 0, 0),
@@ -907,7 +907,7 @@ enum {
MX6_PAD_KEY_ROW0__UART4_RXD = IOMUX_PAD(0x05CC, 0x01FC, 4,
0x0938, 1, 0),
MX6_PAD_KEY_ROW0__GPIO_4_7 = IOMUX_PAD(0x05CC, 0x01FC, 5,
0x0000, 0, 0),
MX6_PAD_KEY_ROW0__DCIC2_DCIC_OUT = IOMUX_PAD(0x05CC, 0x01FC, 6,
0x0000, 0, 0),
- MX6_PAD_KEY_ROW0__PL301_PER1_HADR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7,
0x0000, 0, 0),
+ MX6_PAD_KEY_ROW0__PL301_PER1_HADDR_0 = IOMUX_PAD(0x05CC, 0x01FC, 7,
0x0000, 0, 0),
MX6_PAD_KEY_COL1__ECSPI1_MISO = IOMUX_PAD(0x05D0, 0x0200, 0,
0x07F8, 2, 0),
MX6_PAD_KEY_COL1__ENET_MDIO = IOMUX_PAD(0x05D0, 0x0200, 1,
0x0840, 1, 0),
MX6_PAD_KEY_COL1__AUDMUX_AUD5_TXFS = IOMUX_PAD(0x05D0, 0x0200, 2,
0x07E0, 1, 0),
@@ -916,7 +916,7 @@ enum {
MX6_PAD_KEY_COL1__UART5_TXD_RXD = IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940,
0, 0),
MX6_PAD_KEY_COL1__GPIO_4_8 = IOMUX_PAD(0x05D0, 0x0200, 5,
0x0000, 0, 0),
MX6_PAD_KEY_COL1__USDHC1_VSELECT = IOMUX_PAD(0x05D0, 0x0200, 6,
0x0000, 0, 0),
- MX6_PAD_KEY_COL1__PL301MX_PER1_HADR_1 = IOMUX_PAD(0x05D0, 0x0200, 7,
0x0000, 0, 0),
+ MX6_PAD_KEY_COL1__PL301_PER1_HADDR_1 = IOMUX_PAD(0x05D0, 0x0200, 7,
0x0000, 0, 0),
MX6_PAD_KEY_ROW1__ECSPI1_SS0 = IOMUX_PAD(0x05D4, 0x0204, 0,
0x0800, 2, 0),
MX6_PAD_KEY_ROW1__ENET_COL = IOMUX_PAD(0x05D4, 0x0204, 1,
0x0000, 0, 0),
MX6_PAD_KEY_ROW1__AUDMUX_AUD5_RXD = IOMUX_PAD(0x05D4, 0x0204, 2,
0x07CC, 1, 0),
@@ -940,7 +940,7 @@ enum {
MX6_PAD_KEY_ROW2__USDHC2_VSELECT = IOMUX_PAD(0x05DC, 0x020C, 4,
0x0000, 0, 0),
MX6_PAD_KEY_ROW2__GPIO_4_11 = IOMUX_PAD(0x05DC, 0x020C, 5,
0x0000, 0, 0),
MX6_PAD_KEY_ROW2__HDMI_TX_CEC_LINE = IOMUX_PAD(0x05DC, 0x020C, 6,
0x088C, 1, 0),
- MX6_PAD_KEY_ROW2__PL301_PER1_HADR_4 = IOMUX_PAD(0x05DC, 0x020C, 7,
0x0000, 0, 0),
+ MX6_PAD_KEY_ROW2__PL301_PER1_HADDR_4 = IOMUX_PAD(0x05DC, 0x020C, 7,
0x0000, 0, 0),
MX6_PAD_KEY_COL3__ECSPI1_SS3 = IOMUX_PAD(0x05E0, 0x0210, 0,
0x080C, 1, 0),
MX6_PAD_KEY_COL3__ENET_CRS = IOMUX_PAD(0x05E0, 0x0210, 1,
0x0000, 0, 0),
MX6_PAD_KEY_COL3__HDMI_TX_DDC_SCL = IOMUX_PAD(0x05E0, 0x0210, 2,
0x0890, 1, 0),
@@ -948,7 +948,7 @@ enum {
MX6_PAD_KEY_COL3__I2C2_SCL = IOMUX_PAD(0x05E0, 0x0210, 20,
0x08A0, 1, 0),
MX6_PAD_KEY_COL3__GPIO_4_12 = IOMUX_PAD(0x05E0, 0x0210, 5,
0x0000, 0, 0),
MX6_PAD_KEY_COL3__SPDIF_IN1 = IOMUX_PAD(0x05E0, 0x0210, 6,
0x0914, 2, 0),
- MX6_PAD_KEY_COL3__PL301_PER1_HADR_5 = IOMUX_PAD(0x05E0, 0x0210, 7,
0x0000, 0, 0),
+ MX6_PAD_KEY_COL3__PL301_PER1_HADDR_5 = IOMUX_PAD(0x05E0, 0x0210, 7,
0x0000, 0, 0),
MX6_PAD_KEY_ROW3__OSC32K_32K_OUT = IOMUX_PAD(0x05E4, 0x0214, 0,
0x0000, 0, 0),
MX6_PAD_KEY_ROW3__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05E4, 0x0214, 1,
0x07B0, 0, 0),
MX6_PAD_KEY_ROW3__HDMI_TX_DDC_SDA = IOMUX_PAD(0x05E4, 0x0214, 2,
0x0894, 1, 0),
@@ -956,7 +956,7 @@ enum {
MX6_PAD_KEY_ROW3__I2C2_SDA = IOMUX_PAD(0x05E4, 0x0214, 20,
0x08A4, 1, 0),
MX6_PAD_KEY_ROW3__GPIO_4_13 = IOMUX_PAD(0x05E4, 0x0214, 5,
0x0000, 0, 0),
MX6_PAD_KEY_ROW3__USDHC1_VSELECT = IOMUX_PAD(0x05E4, 0x0214, 6,
0x0000, 0, 0),
- MX6_PAD_KEY_ROW3__PL301_PER1_HADR_6 = IOMUX_PAD(0x05E4, 0x0214, 7,
0x0000, 0, 0),
+ MX6_PAD_KEY_ROW3__PL301_PER1_HADDR_6 = IOMUX_PAD(0x05E4, 0x0214, 7,
0x0000, 0, 0),
MX6_PAD_KEY_COL4__CAN2_TXCAN = IOMUX_PAD(0x05E8, 0x0218, 0,
0x0000, 0, 0),
MX6_PAD_KEY_COL4__IPU1_SISG_4 = IOMUX_PAD(0x05E8, 0x0218, 1,
0x0000, 0, 0),
MX6_PAD_KEY_COL4__USBOH3_USBOTG_OC = IOMUX_PAD(0x05E8, 0x0218, 2,
0x0944, 1, 0),
@@ -973,7 +973,7 @@ enum {
MX6_PAD_KEY_ROW4__UART5_CTS = IOMUX_PAD(0x05EC, 0x021C, 4,
0x093C, 1, 0),
MX6_PAD_KEY_ROW4__GPIO_4_15 = IOMUX_PAD(0x05EC, 0x021C, 5,
0x0000, 0, 0),
MX6_PAD_KEY_ROW4__MMDC_DEBUG_50 = IOMUX_PAD(0x05EC, 0x021C, 6, 0x0000,
0, 0),
- MX6_PAD_KEY_ROW4__PL301_PER1_HADR_8 = IOMUX_PAD(0x05EC, 0x021C, 7,
0x0000, 0, 0),
+ MX6_PAD_KEY_ROW4__PL301_PER1_HADDR_8 = IOMUX_PAD(0x05EC, 0x021C, 7,
0x0000, 0, 0),
MX6_PAD_GPIO_0__CCM_CLKO = IOMUX_PAD(0x05F0, 0x0220, 0,
0x0000, 0, 0),
MX6_PAD_GPIO_0__KPP_COL_5 = IOMUX_PAD(0x05F0, 0x0220, 2,
0x08E8, 0, 0),
MX6_PAD_GPIO_0__ASRC_ASRC_EXT_CLK = IOMUX_PAD(0x05F0, 0x0220, 3,
0x07B0, 1, 0),
@@ -1402,7 +1402,7 @@ enum {
MX6_PAD_NANDF_CS1__USDHC3_VSELECT = IOMUX_PAD(0x06D0, 0x02E8, 2,
0x0000, 0, 0),
MX6_PAD_NANDF_CS1__PCIE_CTRL_DIAG_STATUS_BUS_MUX_3 =
IOMUX_PAD(0x06D0, 0x02E8, 4, 0x0000, 0, 0),
MX6_PAD_NANDF_CS1__GPIO_6_14 = IOMUX_PAD(0x06D0, 0x02E8, 5,
0x0000, 0, 0),
- MX6_PAD_NANDF_CS1__PL301_PER1_HRDYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7,
0x0000, 0, 0),
+ MX6_PAD_NANDF_CS1__PL301_PER1_HREADYOUT = IOMUX_PAD(0x06D0, 0x02E8, 7,
0x0000, 0, 0),
MX6_PAD_NANDF_CS2__RAWNAND_CE2N = IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000,
0, 0),
MX6_PAD_NANDF_CS2__IPU1_SISG_0 = IOMUX_PAD(0x06D4, 0x02EC, 1,
0x0000, 0, 0),
MX6_PAD_NANDF_CS2__ESAI1_TX0 = IOMUX_PAD(0x06D4, 0x02EC, 2,
0x0874, 1, 0),
--
1.8.1.2
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