The K1 device tree describes separate functional and bus clocks for TWSI controllers, but the SPL clock tree currently only provides their functional clocks.
Add the bus clocks for TWSI2 and TWSI8, which are the TWSI controllers currently used in SPL, along with their required parent clock chain. TWSI8 uses a fixed-factor bus clock because its write-only clock control register requires the functional and bus gate bits to remain combined in a single clock instance. Signed-off-by: Junhui Liu <[email protected]> --- drivers/clk/spacemit/clk-k1.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/clk/spacemit/clk-k1.c b/drivers/clk/spacemit/clk-k1.c index 07adc126ee39..e239ffe6ba0d 100644 --- a/drivers/clk/spacemit/clk-k1.c +++ b/drivers/clk/spacemit/clk-k1.c @@ -154,11 +154,27 @@ CCU_GATE_DEFINE(CLK_PLL1_409P6, pll1_d6_409p6, pll1_d6_409p6, "pll1_d6", MPMU_ACGR, BIT(0), 0); CCU_GATE_DEFINE(CLK_PLL1_307P2, pll1_d8_307p2, pll1_d8_307p2, "pll1_d8", MPMU_ACGR, BIT(13), 0); +CCU_FACTOR_GATE_DEFINE(CLK_PLL1_102P4, pll1_d24_102p4, pll1_d24_102p4, + "pll1_d8", MPMU_ACGR, BIT(12), 3, 1); +CCU_FACTOR_GATE_DEFINE(CLK_PLL1_51P2, pll1_d48_51p2, pll1_d48_51p2, + "pll1_d8", MPMU_ACGR, BIT(7), 6, 1); +CCU_FACTOR_GATE_DEFINE(CLK_PLL1_25P6, pll1_d96_25p6, pll1_d96_25p6, + "pll1_d8", MPMU_ACGR, BIT(4), 12, 1); CCU_FACTOR_GATE_DEFINE(CLK_PLL1_31P5, pll1_d78_31p5, pll1_d78_31p5, "pll1_d4", MPMU_ACGR, BIT(6), 39, 2); CCU_DDN_DEFINE(CLK_SLOW_UART2, slow_uart2_48, slow_uart2_48, "pll1_d4_614p4", MPMU_SUCCR_1, CCU_DDN_MASK(16, 13), 16, CCU_DDN_MASK(0, 13), 0, 2, 0); + +static const char * const apb_parents[] = { + "pll1_d96_25p6", + "pll1_d48_51p2", + "pll1_d96_25p6", + "pll1_d24_102p4", +}; + +CCU_MUX_DEFINE(CLK_APB, apb_clk, apb_clk, apb_parents, ARRAY_SIZE(apb_parents), + MPMU_APBCSCR, 0, 2, 0); #else CCU_GATE_DEFINE(CLK_PLL1_307P2, pll1_d8_307p2, pll1_d8_307p2, "pll1_d8", MPMU_ACGR, BIT(13), 0); @@ -306,6 +322,9 @@ CCU_MUX_GATE_DEFINE(CLK_TWSI2, twsi2_clk, twsi2_clk, twsi_parents, */ CCU_GATE_DEFINE(CLK_TWSI8, twsi8_clk, twsi8_clk, "pll1_d78_31p5", APBC_TWSI8_CLK_RST, BIT(1) | BIT(0), 0); +CCU_GATE_DEFINE(CLK_TWSI2_BUS, twsi2_bus_clk, twsi2_bus_clk, "apb_clk", + APBC_TWSI2_CLK_RST, BIT(0), 0); +CCU_FACTOR_DEFINE(CLK_TWSI8_BUS, twsi8_bus_clk, twsi8_bus_clk, "apb_clk", 1, 1); #else static const char * const uart_clk_parents[] = { @@ -1232,8 +1251,12 @@ static struct clk *k1_ccu_mpmu_clks[] = { &pll1_d4_614p4.common.clk, &pll1_d6_409p6.common.clk, &pll1_d8_307p2.common.clk, + &pll1_d24_102p4.common.clk, + &pll1_d48_51p2.common.clk, + &pll1_d96_25p6.common.clk, &pll1_d78_31p5.common.clk, &slow_uart2_48.common.clk, + &apb_clk.common.clk, }; #else static struct clk *k1_ccu_mpmu_clks[] = { @@ -1288,6 +1311,8 @@ static struct clk *k1_ccu_apbc_clks[] = { &uart0_clk.common.clk, &twsi2_clk.common.clk, &twsi8_clk.common.clk, + &twsi2_bus_clk.common.clk, + &twsi8_bus_clk.common.clk, }; #else static struct clk *k1_ccu_apbc_clks[] = { -- 2.55.0
