On Mon, 2026-11-02 at 10:42 -0600, David Lechner wrote:
> On 10/30/26 3:57 AM, Steffen Dirkwinkel wrote:
> > From: Steffen Dirkwinkel <[email protected]>
> > 
> > Device tree walks and other setup is very slow without caches, so turn
> > them on before relocation.
> > 
> > On an MT8370 module, from bootstage marks before each initcall, two
> > boots each:
> > 
> >   step                            caches off        caches on
> >   initf_dm                        349.8 / 349.7     4.6 / 4.6 ms
> >   serial_init                     204.7 / 204.7     3.0 / 3.0 ms
> >   dram_init                       162.2 / 162.1     2.3 / 2.3 ms
> >   relocate_code                   22.0 / 22.0       0.4 / 0.4 ms
> >   board_init_f() to main_loop()   819 / 819         87 / 87 ms
> > 
> > and from the serial console, after power-on (includes 5s debug usb wait):
> > 
> >   U-Boot banner                   7346 / 7346 ms    6772 / 6777 / 6765 ms
> > 
> > Signed-off-by: Steffen Dirkwinkel <[email protected]>
> > ---
> >  arch/arm/mach-mediatek/cpu.c         | 14 ++++++++++++++
> >  arch/arm/mach-mediatek/mt8188/init.c | 23 ++++++++++++++++++++---
> >  2 files changed, 34 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm/mach-mediatek/cpu.c b/arch/arm/mach-mediatek/cpu.c
> > index 04ede8823b07..484a50f0a25c 100644
> > --- a/arch/arm/mach-mediatek/cpu.c
> > +++ b/arch/arm/mach-mediatek/cpu.c
> > @@ -7,10 +7,13 @@
> >  #include <dm.h>
> >  #include <init.h>
> >  #include <wdt.h>
> > +#include <asm/global_data.h>
> >  #include <dm/uclass-internal.h>
> >  #include <linux/arm-smccc.h>
> >  #include <linux/types.h>
> >  
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> >  #define MTK_SIP_PLAT_BINFO ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, 
> > ARM_SMCCC_SMC_64, \
> >                                           ARM_SMCCC_OWNER_SIP, 0x529)
> >  
> > @@ -23,6 +26,17 @@ int arch_cpu_init(void)
> >  
> >  void enable_caches(void)
> >  {
> > +#if IS_ENABLED(CONFIG_TARGET_MT8188) && !IS_ENABLED(CONFIG_XPL_BUILD) && \
> > +   !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
> 
> instead of checking CONFIG_TARGET_MT8188, this would become the same config
> option I suggested in the previous patch so that we don't have to keep adding
> additional targets.
> 
> And U-boot preferred style is to use if statement instead of #if preprocessor
> for things like this. The the compiler will still optimize it out the same.

I didn't do a generic implementation before, because I can only test on mt8188.
But it would be cleaner than doing the same thing for all SOCs and there is
still the DCACHE_OFF kconfigs to enable/disable it, so I'll make it generic in
v2.

> 
> > +   /* Deactivate the data cache, enabled before relocation in 
> > mach_cpu_init() */
> > +   dcache_disable();
> > +   /*
> > +    * Force the call of setup_all_pgtables() in mmu_setup() by clearing
> > +    * tlb_fillptr, to use the page tables reserved by arch_reserve_mmu()
> > +    */
> > +   gd->arch.tlb_fillptr = 0;
> > +#endif
> > +
> >     /* Enable D-cache. I-cache is already enabled in start.S */
> >     dcache_enable();
> >  }
> > diff --git a/arch/arm/mach-mediatek/mt8188/init.c 
> > b/arch/arm/mach-mediatek/mt8188/init.c
> > index 2e6aa041c38f..139412071131 100644
> > --- a/arch/arm/mach-mediatek/mt8188/init.c
> > +++ b/arch/arm/mach-mediatek/mt8188/init.c
> 
> And similarly, we should try to avoid this target-specific boilerplate that
> would have to be repeated for every target.
> 
> > @@ -49,15 +49,32 @@ int print_cpuinfo(void)
> >     return 0;
> >  }
> >  
> > -#if IS_ENABLED(CONFIG_XPL_BUILD) && !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
> > +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
> >  /* Early page tables, in DRAM unused by SPL and by U-Boot before 
> > relocation */
> >  #define MT8188_EARLY_TLB_ADDR      0x4e000000
> >  
> > -/* Initialize the MMU and activate the data cache in SPL */
> > -void mtk_spl_enable_caches(void)
> > +/*
> > + * Initialize the MMU and activate the data cache in SPL and in the U-Boot
> > + * pre-reloc stage. The MMU/TLB is updated in enable_caches() after 
> > relocation.
> > + */
> > +static void mt8188_enable_early_caches(void)
> >  {
> >     gd->arch.tlb_addr = MT8188_EARLY_TLB_ADDR;
> >     gd->arch.tlb_size = PGTABLE_SIZE;
> >     dcache_enable();
> >  }
> > +
> > +#if IS_ENABLED(CONFIG_XPL_BUILD)
> > +void mtk_spl_enable_caches(void)
> > +{
> > +   mt8188_enable_early_caches();
> > +}
> > +#else
> > +int mach_cpu_init(void)
> > +{
> > +   mt8188_enable_early_caches();
> > +
> > +   return 0;
> > +}
> > +#endif
> >  #endif
> > 

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