This paper states that this issue is caused by the (ARM specific) cache
on the logical address space.
What should be expected for other architectures? How is cache designed
on PPC and intel platforms? Are there differencies to expect?
I might be wrong, but AFAIK, ARM is the only architecture that uses
logical addresses instead of physical addresses in the cache and thus
needs flushing the cache with any task switch (that needs updating the
MMU). If physical addresses are used in the cache, same obviously is
independent of what the CPU changes in the MMU and also can be used by
DMA that bypasses the MMU. If there are multiple caches (e.g with
multiple CPUs) there needs to be complex hardware to ensure the data
integrity between the caches. If there are DMA controllers that access
the memory without using the cache, this needs to be handled
appropriately, too.
-Michael
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