Hi Josef,
Wolf, Josef wrote:
rwarner wrote:
Have you seen this paper on why an mmu might not be wanted in
a embedded system?
http://www.linuxdevices.com/articles/AT2598317046.html
also in .pdf @
http://opensrc.sec.samsung.com/document/uc-linux-04_sait.pdf
I've also thought that the memory page swapping technique for paging
in
new memory for execution was costly. This paper shows this well.
This paper states that this issue is caused by the (ARM specific) cache
on the logical address space.
What should be expected for other architectures? How is cache designed
on PPC and intel platforms? Are there differencies to expect?
It varies across the family members in most architectures.
Newer cores in the ARM family are not virtually tagged either.
But all processors running with virtual memory will have to
deal with a TLB, and the extra cycle costs associated with
TLB misses. As well as the work required to create and manage
the page tables.
Now of course there are many downsides to not having VM too.
That puts real limitations on some things (forking for example,
memory fragmentation, etc). No doubt on some work loads though
it can perform better.
Regards
Greg
------------------------------------------------------------------------
Greg Ungerer -- Chief Software Dude EMAIL: [EMAIL PROTECTED]
SnapGear -- a Secure Computing Company PHONE: +61 7 3435 2888
825 Stanley St, FAX: +61 7 3891 3630
Woolloongabba, QLD, 4102, Australia WEB: http://www.SnapGear.com
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