Hi Brian, There's a supported method to include OOT repos that can build and include xilinx IP (or basically any other IP that you need, including HLS. I've yet to try it with sysgen blocks, but that would probably work too). Basically you can use uhd_image_builder.py or uhd_image_builder_gui.py to include a Makefile.inc from an OOT repo, rather than copying the text from the Makefile.srcs.
See my repo here for a minimal basic example: https://github.com/ejk43/rfnoc-ootexample There's also an open source FPGA polyphase channelizer OOT module that uses this approach: https://github.com/e33b1711/rfnoc-ppchan Good luck! Let me know if this helps Best regards, EJ On Feb 26, 2018 2:37 PM, "Brian Padalino via USRP-users" < usrp-users@lists.ettus.com> wrote: > Hi, > > I'm trying to add a piece of Xilinx IP using an .xci file, similar to how > the normal flow for the FPGA build goes, but I want to keep it associated > with my OOT source, and not change the main FPGA repository. > > I haven't found any instructions on how to do this, so I figure I'd ask > here. > > Is it as simple as adding a .xci file to the list of sources and having it > build? The normal FPGA build seems to go through a lot more steps to > generate all the IP and list their simulation and synthesis sources. > > Guidance is appreciated on how to do this "correctly" with an OOT module. > > Thanks, > Brian > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
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