Thanks for the response. I don´t want to run the software component of the GNSS receiver on my computer, while connected to the N310 for heterogeneous processing - if that's what you're saying. I want an edge device running embedded linux, like I already have on my zcu102, to run both sw and hw components.
The first stages of the processing chain are in hardware so I don´t want to read samples from the front-end at the application level. I want to read samples directly from my hardware block design, do some heavy processing and deliver the results to the software application. I can do all of this using AD front-ends and their HDL reference designs. Is there any support to do this using N210 or N310? Thanks again. On Tue, 3 Jan 2023 at 15:15, Marcus Müller <marcus.muel...@ettus.com> wrote: > Note that the N310's FPGA might actually be large enough to fit in (parts > of) a GNSS receiver, especially if you remove the DUC chain of the TX path, > in case you don't need that. RFNoC is Ettus' framework for extending the > FPGA functionality, especially made for such use cases. > > Note that even in RFNoC you get a stream of samples from the radio > frontend, which you basically paid NI/Ettus for to design it for you, so > that you don't have to worry about how to talk to the physical hardware and > can care about signal processing :) > > Cheers, > Marcus > > On 03.01.23 16:11, Marcus Müller wrote: > > Hi Mr Pereira, > > the directest access you get to samples in the N210 is the ethernet > connection – and that has no downside for GNSS applications, as the VITA49 > samples fully represent the RF signal, thanks to Shannon-Nyquist. > > That is, of course, unless you start modifying the FPGA image of the N210, > and make it a completely different product. It's kind of unlikely you want > to do that. > > Greetings, > Marcus > > On 03.01.23 14:25, Pedro Pereira wrote: > > Greetings, > > I have 2 USRP front-ends - N210 and N310. I want to develop a GNSS > Receiver inside my FGPA - xilinx ZCU102 - and use one of the USRP devices > only as the front-end. The receiver is quite large so I need an external > board for all the signal processing chain. The receiver has two > implementations - software-only & hybrid. In hybrid mode some tasks of the > processing chain are accelerated in hardware. > > The software-only version of the receiver running on my ZCU102 is able to > configure the N210 and read packets over ethernet correctly. However, with > the hybrid version of the receiver, I want to read the digital IQ samples > from the front end directly in hardware. > > For example, I am able to do this with the ZCU102 connected to FMComm2/3 > using the FMC connection on the FPGA. AD provides HDL reference designs to > support communication between multiple front-ends and multiple FPGAs. > > Is there a similar way to read the digital samples directly in hardware > using the N210? The N210 only has the ethernet and a MIMO port. > > Thanks in advance. > > > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com > > _______________________________________________ > USRP-users mailing list -- usrp-users@lists.ettus.com > To unsubscribe send an email to usrp-users-le...@lists.ettus.com >
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