On Wed, 2016-09-07 at 10:23 +0200, Julian Seward wrote: > Yes, I have seen AVX-512 looming on the horizon for a while. Yes, we > should support it. Dealing with AVX/AVX2 was a lot of work, and there is > not much AVX-512 available hardware out there, which may explain the > relative lack of activity so far. > > I would be willing to make the infrastructural changes in VEX and Valgrind > necessary to provide a framework in which we can incrementally add support > for individual instructions. That would be: addition of support for 512 > bit registers, changes in the front end instruction decoding framework, and > changes in the back end (if any required, possibly none). > > One problem is the lack of hardware. As I understand it, some but not > all Skylake CPUs support AVX-512. Having said that, if you are really > looking for a working implementation on Knights Landing then it would > be necessary to test any implementation both on Skylake+AVX512 and > Knights Landing. > > A good description of the instruction set is also necessary. Is that > publically available? > > Can you make available, reliable, administrative-hassle-free > remote access to a box that supports AVX-512? Assuming there is an access to an AVX512 box, I can take in charge the updates needed for valgrind gdbserver.
Note that one admin hassle free way to provide such a box is for intel to donate such a box to gcc compile farm (and maybe even better, to host it). Philippe ------------------------------------------------------------------------------ _______________________________________________ Valgrind-users mailing list Valgrind-users@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/valgrind-users
