On Jun 27, 2011, at 18:32, Bill Sommerfeld wrote:
> On 06/27/11 15:24, David Magda wrote:
>> Given the amount of transistors that are available nowadays I think
>> it'd be simpler to just create a series of SIMD instructions right
>> in/on general CPUs, and skip the whole co-processor angle.
>
> see: http://en.wikipedia.org/wiki/AES_instruction_set
>
> Present in many current Intel CPUs; also expected to be present in AMD's
> "Bulldozer" based CPUs.
Now compare that with the T-series stuff that also handles 3DES, RC4, RSA2048,
DSA, DH, ECC, MD5, SHA1, SHA2, as well as a hardware RNG:
http://en.wikipedia.org/wiki/UltraSPARC_T2
http://blogs.oracle.com/BestPerf/entry/20100920_sparc_t3_pk11rsaperf
The initial TLS/SSL set up is actually the expensive part (20-58% of the time
spent of the 'transaction'), and that AES can be performed decently even on
non-AESNI CPUs: simply adding an RSA accelerator can double performance without
session caching, and even ~20% with it. SSL session caching alone can help
improve throughput by a factor of more than two.
"Performance Analysis of TLS Web Servers"
http://www.cs.rice.edu/~dwallach/pub/tls-tocs.pdf
http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.16.1403
AESNI is certain better than nothing, but RSA, SHA, and the RNG would be nice
as well. It'd also be handy for ZFS crypto in addition to all the network IO
stuff.
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