On 09/19/2014 11:06 AM, Slichter, Daniel H. wrote:
> I heartily agree on all counts.  However, for back compatibility with
> current DDS and TTL breakout boards I thought we should at least have
> the option.  We can use commericial SCSI cables to improve the
> reliability over the current homemade ribbon cable method.
> Furthermore, I have done some looking into various chips to do
> serialization/deserialization to enable us to use high speed serial
> for the FPGA-DDS and FPGA-TTL connections.  The issue is that almost
> all the chips I found have nondeterministic latencies from chip to
> chip, and I worry about all the effort we are putting in to making a
> nice RTIO core if in the end we are limited by the performance of the
> deserialization at the end (jitter of +/- 1 slow (parallel) clock
> cycle is a typical spec as well).

I fear you have your terminology confused up here. A jitter of one
parallel UI is unlikely.

Anyway. Latencies are already non-deterministic in our setups. Worse,
they are unknown and uncontrolled. We need a return channel anyway to
pin them down. And once you have a return channel you can use any
physical layer.

> If we are able to find a suitable technical solution for the SERDES,
> my thought for high speed serial would be to use DisplayPort
> connectors and cables, which have 4 differential pairs and can be
> used for long (3 m) runs at full bandwidth (~8 Gbit/s for DisplayPort
> 1.0, more than we likely need).

DisplayPort is pretty much one-way. If you really need that many lanes
and that data rate, something like SNAP12 would do it. Optical layers
have the advantage of much longer lengths and galvanic isolation.

> There exist chipsets which implement specific SERDES protocols (e.g.
> HDMI, DisplayPort) but the latencies and jitter associated with these
> are even worse.  For the applications for which they are used, there
> just isn't much incentive to care about absolute timing to the degree
> we need.

Robert.
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