This draft document, entitled Register Constraint Relief 2021, coincidentally addresses the subject of Base-less/Base-free Macros. See references to Base Address Register (BAR) 15 and relative addressing for all base/displacement operands..
https://docs.google.com/document/d/19O8Z-H3XcgiDWOI_zO4NM8JnRHllGn91sFTDtgQ39bc/edit?usp=sharing OREXXMan Would you rather pass data in move mode (*nix piping) or locate mode (Pipes) or via disk (JCL)? Why do you think you rarely see *nix commands with more than a dozen filters, while Pipelines specifications are commonly over 100s of stages, and 1000s of stages are not uncommon. REXX is the new C. On Wed, Nov 10, 2021 at 3:02 AM Jonathan Scott <jonathan_sc...@vnet.ibm.com> wrote: > The documentation update for APAR PH34824, for the alignment of > literals referenced by relative address, has now been completed. > > https://www.ibm.com/docs/en/hla-and-tf/1.6?topic=instruction-literal-pool > > It seems it was overlooked after being transferred from our old > request tool to the new - a case of "falling between two tools". > > Jonathan Scott, HLASM > IBM Hursley, UK >
