Chris R. Anderson wrote:
At 03:06 PM 8/5/2008, you wrote:On Tue, Aug 5, 2008 at 2:45 PM, Chris R. Anderson <[EMAIL PROTECTED]> wrote:> Brian -- Thanks for the suggestions on the FPGA. We've been using the > Altera parts up here for several years now, so our guys are definitely> familiar with the development process. Personally, I'm leaning towards the > EP3C16 to help keep the costs down. We're probably going to use the AD9862 > ADC/DAC (which is basically the same thing used on the USRP), which retails> for $57.75 on Digikey.No problem, and sounds good. It definitely is pretty darn cheap for the resources you get. As for the ADC/DAC, do you plan on trying to do the full 64MSPS processing? How much bandwidth are you looking to process?What I'd like to do is run a 64 MHz clock into one of the PLLs on the FPGA, and let the FPGA control the clock speed of the ADC/DAC. That way you have some reasonable control over the sampling rate/bandwidth you want to work with. Ideally, I'd like to be able to process as much bandwidth as possible, but I suspect the limitation will be the interface to the Beagleboard. Most of the commercial radios seem to max out at around 20 MHz, if we could get even 1/4 of that (5 MHz), I think we would be doing pretty good.
I suspect that sampling at 64 MHz is the best approach. The existing USRP daughterboards all make this assumption. We can do sample rate conversions in the FPGA. I'd like to make as much BW available to the FPGA as possible and let users decide how to process it.
With trying to keep costs down, using the same AFE as the USRP seems like it isn't that good of an idea mainly due to the fact that it is built on old technology and costs so much.I guess I should clarify that we'd like to use the same daughterboard connector as the USRP. I agree that its older technology and may not be the best solution, but it does give us a working AFE to start with. Our guys get lots of digital design experience, but absolutely zero RF design experience--which I learned the hard way last year. Using the USRP AFE means one less thing we have to worry about debugging.
I am familiar with the existing part, and we can see how the USRP interfaces with it. Using it reduces risk in my eyes. Looking into data converter alternatives would be a good exercise for your students, but as we know, there are lots of choices :) Also the transmit path signal processing is mostly done in the AD part, saving space in the FPGA for RX processing.
The upside to this approach is that we're not strictly limited to using USRP AFE's: any board that matches the pinout could be substituted instead. The limitation is that the ADC has to be separated from the AFE. I'm not dead-set on going down this route, however. If we could find a good RF designer that wanted to create a custom AFE for the board, it would certainly be worth entertaining the idea.
Re-using the existing daughterboards is pretty key here. Without the daughterboard support, you may as well hang a dev board off the expansion connector and cobble together some RF from mini-circuits parts .
Philip
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