Brian Padalino wrote:
On Wed, Aug 6, 2008 at 8:47 AM, Philip Balister <[EMAIL PROTECTED]> wrote:
I suspect that sampling at 64 MHz is the best approach. The existing USRP
daughterboards all make this assumption. We can do sample rate conversions
in the FPGA. I'd like to make as much BW available to the FPGA as possible
and let users decide how to process it.
Understandable with regards to the bandwidth and wanting to get as
much into the FPGA as possible, but the daughterboards know nothing
about the sample frequency. Looking at the dboard connector, there is
no LO or reference clock going up to that header (from what I saw) -
I think the signal line "clock_p", J1, pin 11 carries a 64MHz clock
from the motherboard up to the daughterboard. This serves as a
reference clock to the local oscillator (AD4360 integrated synthesizer
and VCO) chip on the daughterboard. Having said this, there is a
placeholder for a 10MHz reference oscillator on the daughterboard though
and the user can swap some 0 ohm resistors to use this instead.
just some GPIO digital lines along with some analog lines.
Chris, do you have any price, system performance targets for the
board(s)?
I agree with Brian's suggestion below. Also, if you decide you want a
similar feature set to the 9862 but are willing to consider a lower cost
and performance alternative then I would suggest the 9860.
http://www.analog.com/en/broadband-products/broadband-codecs/AD9860/products/product.html
I think it's a good idea to go through some of these lower cost
devices to see if any of their features mesh better with the actual
subset of features being used on the current USRP, the future USRP2
and within GNU Radio.
Brian
Cheers,
Nikhil
