On Wed, Aug 6, 2008 at 12:46 PM, Nikhil Adnani <[EMAIL PROTECTED]> wrote: > I think the signal line "clock_p", J1, pin 11 carries a 64MHz clock from > the motherboard up to the daughterboard. This serves as a reference clock > to the local oscillator (AD4360 integrated synthesizer and VCO) chip on the > daughterboard. Having said this, there is a placeholder for a 10MHz > reference oscillator on the daughterboard though and the user can swap some > 0 ohm resistors to use this instead.
You're right - I stand corrected. It's probably best to keep that signal 64MHz as all the daughterboard code in GNU Radio probably assumes the reference clock to be 64MHz. On the other hand, I believe the USRP2 is going to be running from a 100MHz clock with compatibility for the current daughterboard set, so it might not be completely necessary to run that clock at 64MHz? On a completely different side tangent on using a PLL in the FPGA to drive the ADC for arbitrary sampling rates, it may end up costing a good amount to make sure the clock ends up being as clean and jitter-free as possible as well as phase aligned for proper setup and hold times for the FPGA<->converter interface. A direct connection from the oscillator to the converter is probably best practice. Brian
