Brian Padalino wrote:
On a completely different side tangent on using a PLL in the FPGA to drive the ADC for arbitrary sampling rates, it may end up costing a good amount to make sure the clock ends up being as clean and jitter-free as possible as well as phase aligned for proper setup and hold times for the FPGA<->converter interface. A direct connection from the oscillator to the converter is probably best practice.
True. I've done some phase noise tests on clocks routed through FPGAs. Even if you're not using the on-chip PLL or DLL, there is significant contamination of the clock spectrum from switching threshold modulation of the internal gates by other logic on the FPGA. This will result in significantly reduced SNR if used for frequency conversion or sampling.
For RF local oscillators and ADC clocks you're best off using a clock source that comes directly from a high-purity source, such as an XO or TCXO. If that's not possible, use a stand-alone PLL which has been specifically designed for low phase noise (wide loop bandwidths, small VCO gain constants, etc).
Eric
